Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
2001-04-06
2004-06-29
Baumeister, Bradley (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S669000, C257S670000, C257S674000, C257S676000
Reexamination Certificate
active
06756658
ABSTRACT:
BACKGROUND
1. Technical Field
This invention pertains to the semiconductor packaging art in general, and in particular, to making two-lead, surface-mounting, high-power, micro-leadframe semiconductor packages having enhanced power ratings and lower manufacturing costs.
2. Related Art
In a known type of high-power, metal-oxide-semiconductor field effect transistor (“MOSFET”) device, a number of lower-power devices are formed in a single semiconductor die, or “chip,” and the respective “gate” and “source” terminals of the devices are all formed on the top of the die and respectively connected in parallel by thin metal pads on the top surface of the die, which in turn, are internally connected, typically by wire bonds, to respective leads of the device package.
The “drain” terminals of the individual devices are all respectively formed on the bottom of the die, and are connected in parallel by a thin metal pad on the bottom surface of the die, which in turn, is internally connected, typically by solder, to a metal die-mounting pad, which then constitutes a third “lead,” or terminal, of the package. Other types of two- and three-terminal, high-power electronic devices can be made in a similar fashion.
An industry standard TO-252 “two-lead header,” surface-mounting, highpower, leadframe semiconductor package
10
adapted to accommodate the above types of devices is illustrated in the top plan, side elevation, and bottom plan views of
FIGS. 1-3
, respectively, in which a protective plastic envelope
36
molded over the device is shown by a dashed line to reveal the underlying details thereof. The standard package
10
, sometimes referred to as a “Dpak” package, is similar to other standardized two-lead, surface-mounting packages of a known type in the industry, viz., the TO-263 (“D2pak”) and the TO-268 (“D3pak”) outline packages.
The lead frame
12
of the standard package
10
comprises a rectangular die pad
14
, three leads
16
,
18
and
20
, and a “header”
22
that are typically die-stamped from a dual-gage metal sheet, e.g., copper. A first, down-set tie-bar
24
permanently connects the vestigial center lead
18
to the die pad
14
, and a second, transverse tie-bar
26
(shown by dashed lines) temporarily connects the three leads
16
,
18
, and
20
together until the package is molded over with plastic, and is then cut away and discarded.
A semiconductor die
28
incorporating an electronic device of the type described above is mounted on the upper surface of the die pad
14
with its lower surface in electrical connection therewith, and a plurality of wire bonds
30
are connected between bonding pads
32
and
34
on the upper surface of the die
28
and right-angled wire bonding arms at the inner ends of each of the first and second leads
16
and
20
, respectively, as described above. A protective plastic envelope
36
is molded over the leadframe
12
, die
28
, and wire bonds
30
, and a lower surface of the die pad
14
is exposed through and flush with the envelope to constitute, along with the down-set first and second leads
16
and
20
, a third, surface-mounting terminal of the package
10
.
While the industry-standard package
10
provides a workable housing and mounting for the above-described types of high-power devices, it also includes some aspects that need improvement. In particular, the dual thickness leadframe
12
is relatively expensive to produce, and is limited to a single inline, or tandem, “strip” production method that is relatively cost-inefficient.
Also, the two leads
16
and
20
of the package
10
must be made relatively thin so that they can be formed in multiple planes, as shown in the figures, and as a result, their electrical conductivity is adversely reduced. Further, the length of the right-angled wire-bonding arms on the inner ends of the leads
16
and
20
is limited by the presence of the third, vestigial lead
18
. As a consequence, only two small (0.008 in.) diameter wire bonds
30
can be made to the second lead
20
of the package, which adversely affects the internal resistance of the package in, e.g., a power MOSFET, resulting in a relatively high value for the internal resistance between the drain and the source of the device during operation (“R
DS(ON)
”), and a concomitant lower power rating for the package.
A need therefore exists for a two-lead, surface-mounting, high-power, micro-leadframe semiconductor package that has the same outline, mounting, and electrical functionality as industry-standard power packages, but which has a higher package power rating and costs less to produce than such packages. This invention provides such a package and a method for making it.
SUMMARY
The novel package of the invention and the method for making it comprise providing a metal plate having a uniform thickness. A rectangular array of identical microstructures, each having parallel and respectively coplanar upper and lower surfaces, are formed in the plate, e.g. by photolithography and etching techniques. Each of the microstructures includes an I-shaped die pad having a head, a foot, and opposite sides. A first, elongate lead is disposed at the foot of the die pad. The first lead has a side aligned with one of the sides of the pad, a proximal end located next to the die pad, and an opposite, distal end. A second, L-shaped lead is also disposed at the foot of the die pad, on the other side thereof from the first lead. The second lead has a side aligned with the second side of the die pad, a proximal end; with an elongated right-angled wire-bonding arm thereon located next to the pad, and an opposite, distal end.
A plurality of disposable tie-bars temporarily couple the die pad and the leads of each microstructure together within the plate during fabrication of the packages. A recessed shoulder can be formed around at least a portion of the periphery of the lower surface of each of the die pad and the leads in each microstructure to provide enhanced moisture resistance of the package and adhesion with a protective plastic envelope molded on the package.
A semiconductor die is mounted with its lower surface on and in electrical connection with the upper surface of the die pad in each of the microstructures, such that the die pad comprises an electrical terminal of the resulting package, e.g., in a power MOSFET device, a drain terminal. A plurality of wire bonds is connected between pads on the upper surface of the dies in each of the microstructures and an upper surface of the proximal ends of each of associated ones of the first and second leads therein to complete the internal electrical connection of the dies. For example, in a power MOSFET package, a single wire bond is connected between a common gate pad on the upper surface of the die and the proximal end of the first lead, and as many as five wire bonds are connected between a common source pad on the die and the right-angled wire-bonding arm on the second lead of the package.
A protective envelope of plastic is molded over the die pad, the leads, the die, and the wire bonds in each of the microstructures in the plate, such that at least a portion of a lower surface of each of the die pads and the leads therein is exposed through a lower surface of a respective plastic envelope to form a separate, flush, surface-mounting terminal of the respective package. After the plastic envelopes are molded on the microstructures, the tie bars holding each microstructure in the plate are cut through around a periphery of the envelope of the respective package to singulate the package from the plate.
By utilizing a single, thicker gage of metal in a micro-leadframe design, rather than the thinner, dual-gage metal of the prior art die-stamped leadframe, and by assembling the packages in a large rectangular array, rather than in the single, inline strip of the prior art method, a substantial reduction in package manufacturing costs results. Additionally, the novel design affords nearly twice the lead thickness, and enables up to three more wire bonds of greater diameter to be made to the le
Boland Bradley D.
Crowley Sean T.
Edwards Keith M.
Gillett Blake A.
Amkor Technology Inc.
Baumeister Bradley
Stetina Brunda Garred & Brucker
Warren Matthew E.
LandOfFree
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