Amplifiers – With semiconductor amplifying device – Including frequency-responsive means in the signal...
Reexamination Certificate
2001-09-10
2004-11-02
Cunningham, Terry D. (Department: 2816)
Amplifiers
With semiconductor amplifying device
Including frequency-responsive means in the signal...
C330S306000, C330S277000, C330S310000
Reexamination Certificate
active
06812794
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a multistage amplifier in which an input signal is amplified stage by stage and is output.
BACKGROUND ART
In a multistage amplifier using a type of semiconductor devices such as field effect transistors (FETs), bipolar junction transistors (BJTs) or hetero junction bipolar transistors (HBTs), an input matching circuit placed on an input side, an output matching circuit placed on an output side and an inter-stage matching circuit placed between the input matching circuit and the output matching circuit are generally arranged so as to bring out the performance of the type of semiconductor devices.
For example,
FIG. 1
is a view of an equivalent circuit of a conventional multistage amplifier disclosed in “Technical Report of the Institute of Electronics, Information and Communication Engineers (IEICE), MW95-73”, published in July of 1995. In
FIG. 1
,
1
indicates an input terminal for receiving a signal.
2
indicates an output terminal for outputting an amplified signal.
3
indicates a front-stage amplifying element for amplifying the signal received in the input terminal
1
.
4
indicates a rear-stage amplifying element for amplifying the signal amplified in the front-stage amplifying element
3
.
5
indicates an input matching circuit of the conventional multistage amplifier.
6
indicates an inter-stage matching circuit for performing an impedance matching between the front-stage amplifying element
3
and the rear-stage amplifying element
4
.
7
indicates a bias circuit.
8
indicates an output matching circuit of the conventional multistage amplifier.
9
indicates a short stub for bias supply.
10
indicates a parallel capacitor.
11
indicates a serial line.
12
indicates a serial capacitor.
Here, each of the front-stage amplifying element
3
and the rear-stage amplifying element
4
is composed of an FET, a BJT, a metal oxide semiconductor field effect transistor (MOSFET), a high electron mobility transistor (HEMT) or an HBT.
Next, an operation will be described below.
When a signal is received in the input terminal
1
, the signal is sent to the front-stage amplifying element
3
through the input matching circuit
5
, and the signal is amplified in the front-stage amplifying element
3
.
Thereafter, the signal amplified in the front-stage amplifying element
3
is sent to the rear-stage amplifying element
4
through the inter-stage matching circuit
6
and the bias circuit
7
, and the signal is amplified in the rear-stage amplifying element
4
.
Thereafter, the signal amplified in the rear-stage amplifying element
4
is output from the output terminal
2
through the output watching circuit
8
.
Here, a function of the inter-stage matching circuit
6
will be described below.
In the inter-stage matching circuit
6
, an impedance matching is performed on a certain reference plane between the front-stage amplifying element
3
and the rear-stage amplifying element
4
so as to make a pair of impedances conjugate to each other on both sides of the reference plane.
FIG. 2
is an explanatory view showing a general example of matching conditions between the front-stage amplifying element
3
and the rear-stage amplifying element
4
of the conventional multistage amplifier.
As shown in
FIG. 2
, an output impedance of the front-stage amplifying element
3
is expressed by S
Y
—
FET
, an impedance (that is, an output load impedance of the front-stage amplifying element
3
) on an output side seen from the front-stage amplifying element
3
is expressed by F
out
, an input impedance of the rear-stage amplifying element
4
is expressed by S
x
—
FET
, an impedance (that is, an input source impedance of the rear-stage amplifying element
4
) on an input side seen from the rear-stage amplifying element
4
is expressed by F
in
.
In cases where a small signal operation is performed in the conventional multistage amplifier, an optimum output load impedance &Ggr;
opt
—
out
of the front-stage amplifying element
3
agrees with a conjugate complex impedance S
Y
—
FET
* of the output impedance S
Y
—
FET
of the front-stage amplifying element
3
, and an optimum input source impedance &Ggr;
opt
—
in
, of the rear-stage amplifying element
4
agrees with a conjugate complex impedance S
X
—
FET
* of the input impedance S
X
—
FET
of the rear-stage amplifying element
4
.
Therefore, in cases where a conjugate complex impedance matching is performed at an output terminal X of the front-stage amplifying element
3
, as shown in FIG.
2
(
b
), the inter-stage matching circuit
6
is designed so as to perform an impedance transformation from the input impedance S
X
—
FET
of the rear-stage amplifying element
4
to the conjugate complex impedance S
Y
—
FET
* of the output impedance S
Y
—
FET
of the front-stage amplifying element
3
.
Also, in cases where a conjugate complex impedance matching is performed at an input terminal Y of the rear-stage amplifying element
4
, as shown in FIG.
2
(
c
), the inter-stage matching circuit
6
is designed so as to perform an impedance transformation from the output impedance S
Y
—
FET
of the front-stage amplifying element
3
to the conjugate complex impedance S
X
—
FET
(=&Ggr;
opt
—
in
) of the input impedance S
X
—
FET
of the rear-stage amplifying element
4
.
Therefore, in cases where no loss occurs in the inter-stage matching circuit
6
, when the conjugate complex impedance matching is performed at the output terminal X of the front-stage amplifying element
3
, the conjugate complex impedance matching can be performed at the input terminal Y of the rear-stage amplifying element
4
simultaneously with the conjugate complex impedance matching at the output terminal X.
However, a level of the input signal transmitted through the multistage amplifier induces the conventional multistage amplifier to perform a large signal operation in a final-stage amplifying element or an amplifying element just before the final-stage amplifying element of the conventional multistage amplifier in place of the small signal operation.
In this case, the output impedance S
Y
—
FET
of the front-stage amplifying element
3
and the input impedance S
X
—
FET
of the rear-stage amplifying element
4
in the large signal operation of the conventional multistage amplifier differ from those in the small signal operation, and optimum impedances, which maximize an efficiency of the conventional multistage amplifier, differ from the input and output impedances S
X
—
FET
and S
Y
—
FET
. Therefore, in the large signal operation, the optimum output load impedance &Ggr;
opt
—
out
of the front-stage amplifying element
3
differs from the conjugate complex impedance S
Y
—
FET
* of the output impedance S
Y
—
FET
of the front-stage amplifying element
3
, and the optimum input source impedance &Ggr;
opt
—
in
of the rear-stage amplifying element
4
differs from the conjugate complex impedance S
X
—
FET
* of the input impedance S
X
—
FET
of the rear-stage amplifying element
4
.
Therefore, in cases where a conjugate complex impedance matching is performed at the output terminal X of the front-stage amplifying element
3
, as shown in FIG.
2
(
b
), the inter-stage matching circuit
6
is designed so as to perform an impedance transformation from the input impedance S
X
—
FET
of the rear-stage amplifying element
4
to the optimum output load impedance &Ggr;
opt
—
out
(≠S
X
—
FET
*) of the front-stage amplifying element
3
. Also, in cases where a conjugate complex impedance matching is performed at the input terminal Y of the rear-stage amplifying element
4
, as shown in FIG.
2
(
c
), the inter-stage matching circuit
6
is designed so as to perform an impedance transformation from the output impedance S
Y
—
FET
of the front-stage amplifying element
3
to the optimum input source impedance &Ggr;
opt
—
in
(≈S
X
—
FET
*) of the rear-stage amplifying element
4
.
In this case, it is impossible for the inter-stage matching circuit
6
to perform the conjugate complex impedance matching at the output te
Ikeda Yukio
Kitabayashi Fumimasa
Mori Kazutomi
Shinjo Shintarou
Birch & Stewart Kolasch & Birch, LLP
Cunningham Terry D.
Mitsubishi Denki & Kabushiki Kaisha
Tra Quan
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