Heterojunction field effect transistor

Details Heterojunction field effect transistor Heterojunction field effect transistor

2002-12-17

2004-08-24

Lee, Hsien Ming (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Light responsive structure

C257S192000, C257S194000, C438S268000, C438S273000

Reexamination Certificate

active

06781163

ABSTRACT:

TECHNICAL FIELD
The present invention relates to field effect transistors including a heterojunction for a channel region, and more particularly relates to countermeasures against variation in threshold voltage of a field effect transistor.
BACKGROUND ART
In recent years, portable communication terminals represented by cellular phones are widely used. Such portable terminals are generally driven by batteries and it is strongly desired to reduce power consumption without sacrificing operation speed in portable terminals in order to prolong the lifetime of batteries. To achieve a portable communication terminal with low power consumption without reducing operation speed, it is effective to increase drain saturation current to maintain current driveability while lowering threshold voltage to reduce supply voltage in the portable terminal. To satisfy such demands, there have been many studies on heterojunction MOS transistors (which will be hereinafter called “hetero MOS”) using as a channel region a material with high-mobility carriers.
In a known MOS transistor, carriers travel along the interface between a gate oxide film and a silicon substrate. Energy level largely fluctuates around the interface between the gate oxide film that is an amorphous layer and the silicon substrate that is a crystal layer. Because of the energy level fluctuation, carriers are easily affected by interface scattering in the known MOS transistor, resulting in problems such as reduction of carrier mobility and increase in noise.
On the other hand, in the hetero MOS, which is a MOS transistor including a semiconductor heterojunction for a channel region, a semiconductor heterojunction interface is formed at a depth with a small distance apart from the gate insulating film of a semiconductor substrate. A channel is formed at the semiconductor heterojunction interface and carriers travel along the channel. The semiconductor heterojunction interface is an interface where crystal layers are joined together, and thus energy level at the interface does not fluctuate widely. Therefore, the influence of interface scattering on carriers is small. Accordingly, the hetero MOS has a great current driveability and an excellent characteristic of reduction in noise. Furthermore, the hetero MOS has another characteristic that its threshold voltage can be lower than that of the known MOS transistor.
Problems to be Solved
However, in the hetero MOS including a heterojunction for a channel region, the channel region is embedded and therefore threshold voltage largely depends on the thickness of an Si cap region.
FIG. 15
illustrates the structure of a known hetero MOS.
As shown in
FIG. 15
, the known hetero MOS
100
includes an Si substrate
101
, a gate insulating film
102
formed on the Si substrate
101
, a gate electrode
103
which is formed of polysilicon containing a p-type impurity of high concentration on the gate insulating film
102
, and a sidewall spacer
104
which is formed on the gate insulating film
102
to cover side faces of the gate electrode
103
. The Si substrate
101
includes p-type source and drain regions
105
and
106
which are formed on both sides of the gate electrode, an n-type Si cap region
107
formed in a region located between the source and drain regions
105
and
106
, an n-type SiGe channel region
108
formed under the Si cap region,
107
an n-type Si buffer region
109
formed under the SiGe channel region
108
, and an n-type Si body region
110
formed under the Si buffer region
109
.
FIG. 16
shows the results obtained from simulations of dependency of threshold voltage on the thickness of the Si cap region
107
in the known hetero MOS
100
.
As shown in
FIG. 16
, as the thickness of the Si cap region
107
is increased, the absolute value for its threshold voltage remarkably increases. In other words, the threshold voltage is remarkably increased. This is because as the position at which the channel is formed (i.e., the interface between the Si cap region
107
and the SiGe channel region
108
) is located a more distance apart from the gate electrode, i.e., further in depth, the potential at the channel changes less enough according to the gate voltage.
In terms of processing, however, the thickness of the Si cap region
107
is reduced through fabrication processes such as an SiO
2
thermal oxide film formation process and a cleaning process, and thus it is very difficult to control the thickness of the Si cap region
107
. Therefore, nonuniformity in the thickness of the Si cap region
107
can be easily caused. Accordingly, variation in threshold voltage is easily caused and therefore there may be cases where a desired operation can not be performed because of increased threshold voltage.
Particularly, in an integrated circuit including a plural number of identical transistors, variation in threshold voltage among the transistors causes gaps of switching time among the transistors. As a result, the timing gaps among the transistors in the integrated circuit occur, so that the integrated circuit may not operate properly. Moreover, under consideration of variation in threshold voltage among the transistors, in order to ensure an operation margin, the latest switching timing should be set as a standard timing and therefore it is difficult to increase in operation speed of the integrated circuit.
DISCLOSURE OF INVENTION
The present invention has been contrived in order to solve the foregoing problems and an object of the present invention is to provide a semiconductor device in which an increase in threshold voltage is suppressed.
A semiconductor device according to the present invention includes: a substrate; a semiconductor layer formed in an upper part of the substrate; a gate insulating film formed on the semiconductor layer; a gate electrode formed on the gate insulating film; first source/drain regions of a first conductivity type formed on both sides of the gate electrode in the semiconductor layer, respectively; a first cap region of the first conductivity type which is formed of a first semiconductor in a region of the semiconductor layer which is located between the first source/drain regions; a first channel region which is formed under the first cap region in the semiconductor layer and formed of a second semiconductor which has a lower potential for carriers at a band edge along which the carriers travel than the corresponding potential of the first semiconductor; and a first body region of a second conductivity type which is formed of a third semiconductor under the first channel region in the semiconductor layer.
The inventive semiconductor has the structure in which the first cap region of the first conductivity type which is formed of the first semiconductor, the first channel region which is formed under the first cap region and of the second semiconductor which has a lower potential for carriers at a band edge along which the carriers travel than the corresponding potential of the first semiconductor, and the first body region of the second conductivity type which is formed of the third semiconductor under the first channel region in the semiconductor layer. Accordingly, it is possible to achieve a semiconductor device in which an increase in threshold voltage according to an increase in the thickness of the first cap region is suppressed.
The gate electrode and the first body electrode may be electrically connected to each other.
Accordingly, when a gate bias voltage is applied to the gate electrode, forward bias voltage at the same level as the gate bias voltage is applied to the first channel region via the first body region. Therefore, when the gate bias is OFF, the inventive semiconductor device is in the same state as a regular MOS transistor, whereas when the gate bias is ON, the first body region is biased in the forward direction as the gate bias voltage is increased, and thus threshold voltage is reduced. That is to say, a semiconductor device which is operable with a lower threshold voltage can be achieved. Moreover, by forming the semi

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