D/A conversion circuit and semiconductor device

Details D/A conversion circuit and semiconductor device D/A conversion circuit and semiconductor device

2002-11-08

2004-02-03

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S154000, C345S055000

Reexamination Certificate

active

06686858

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a D/A conversion (digital-to-analog conversion) circuit (DAC: Digital-Analog Converter). The invention relates, more particularly, to a DAC used in the driving circuit of a semiconductor device and, further, to a semiconductor device using this DAC.
2. Description of the Related Art
Recently, the technique of fabricating a semiconductor device in which semiconductor thin films are formed on a cheap glass substrate, such as, e.g., the technique of fabricating thin film transistors (TFTs) is being rapidly developed. The reason therefor is that the demand for semiconductors (particularly, active matrix liquid crystal display devices and EL display devices) is growing.
An active matrix liquid crystal display device is constituted in such a manner that, in each of several tens of millions to several hundreds of millions of pixel regions disposed in a matrix-like state, a TFT is disposed, so that the charges coming into and going out from the respective pixel elements are controlled by the switching function of the TFTs.
Among such active matrix liquid crystal display devices, a digital driving type active matrix liquid crystal display device is attracting attention as the display devices are becoming more and more precise and minute and as their picture quality is becoming higher and higher.
FIG. 15
shows an outline of the structure of a conventional digital driving type active matrix liquid crystal display device. The conventional digital driving type active matrix liquid crystal display device is comprised, as shown in
FIG. 15
, of a source signal line side shift register
1401
, address lines (a to d)
1402
for the digital signals inputted from the outside, latch circuits
1
(LAT
1
)
1403
, latch circuits
2
(LAT
2
)
1404
, a latch pulse line
1405
, D/A conversion circuits
1406
, gradation voltage lines
1407
, source signal lines (data lines)
1408
, a gate signal line side shift register
1409
, gate signal lines (scanning lines)
1410
and pixel TFTs
1411
. A 4-bit digital driving type active matrix liquid crystal display device is taken up by way of example. The latch circuits
1
1403
and the latch circuits
2
1404
(LAT
1
and LAT
2
) are each shown in the state in which four latch circuits are put together for convenience sake.
The digital signals fed from the outside to the digital signal address lines (a to d)
1402
are successively written into all the LAT
1
1403
in accordance with the timing signals from the source signal line side shift register
1401
. In this specification, all the LAT
1
put together will be genetically called LAT
1
group.
The length of time required for completing the writing of the digital signals into the LAT
1
group is called one line period. In other words, the time interval from the point of time when the writing of the digital signals inputted from the outside into the LAT
1
at the leftmost side is started to the point of time when the writing of the digital signals inputted from the outside into the LAT
1
at the rightmost side is completed, is one line period.
After the writing of the digital signals into the LAT
1
group is terminated, the digital signals thus written into the LAT
1
group are simultaneously transmitted and written into all the LAT
2
1404
, in tune with the operating timing of the source signal line side shift register
1401
, when a latch signal is inputted to the latch pulse line
1405
. In this specification, all the LAT
2
put together will be genetically called LAT
2
group.
Into the LAT
1
group which has finished the transmission of the digital signals to the LAT
2
group, the writing of the digital signals again fed to the digital decoder address lines (a to d)
1402
is successively carried out in accordance with the signals from the source signal line side shift register
1401
.
In step with the start of the second one-line period, the digital signals previously sent out to the LAT
2
group are inputted to the D/A conversion circuits
1406
and converted into analog graduation voltage signals corresponding to the digital signals and then fed to the source signal lines
1408
.
The analog gradation voltage signals are fed to the corresponding source signal lines
1408
for the one-line period. By the scanning signals outputted from the gate signal line side shift register
1409
, the switching of the corresponding pixel TFTs
1411
is carried out, and, by the analog graduation voltage signals from the source signal lines
1411
, the liquid crystal molecules are driven.
By repeating the above-mentioned operation a number of times equal to the scanning line number, one picture (one frame) is formed. Generally, in an active matrix liquid crystal display device, the rewrite of 60 frame images is effected for one second.
Here, the known A/D converter circuits used in the above-mentioned digital driving circuit will be described.
FIG. 16
will be referred to.
A known 4-bit D/A conversion circuit comprises switches (sw
0
to sw
15
) and gradation voltage lines (V
0
to V
15
). This 4-bit D/A conversion circuit is constituted in such a manner that, by the 4-bit digital signals fed from the LAT
2
group
1404
in the digital driving type active matrix liquid crystal display device shown in
FIG. 15
, one of the switches (sw
0
to sw
15
) is selected, and, from the gradation voltage line connected to the thus selected switch, the voltage is fed to the source signal line
1408
.
In case of the known 4-bit D/A conversion circuit which is now being described, the number of the switches is
16
, and the number of the graduation voltage lines is
16
. In an actual active matrix type liquid crystal display device, the area of the switches themselves is large. Further, the D/A conversion circuit shown in
FIG. 16
is provided at a rate of one to one source signal line, so that the area of the whole driving circuit becomes large.
Another example of the known 4-bit D/A conversion circuit will next be taken up. The 4-bit D/A conversion circuit shown in
FIG. 17
is constituted in such a manner that, as in case of the 4-bit D/A conversion circuit described above, one of a plurality of switches (sw
0
to sw
15
) is selected by the 4-bit digital signal fed from the LAT
2
group
1404
, and, from the gradation voltage line connected to the thus selected switch, the voltage is fed to the source signal line
1408
.
In the D/A conversion circuit shown in
FIG. 17
, the graduation voltage lines are five in number (V
0
to V
4
) and thus are smaller in number than those of a 4-bit D/A conversion circuit as shown in FIG.
16
. However, the number of the switches is still sixteen. Therefore, it is difficult to reduce the area of the whole driving circuit.
In case of a D/A conversion circuit which converts 4-bit digital signals into an analog gradation voltage signal as described here, if the bit number increases, the number of the switches is exponentially increased. In other words, in the known D/A conversion circuit which converts n-bit digital signals into an analog gradation signal, 2
n
switches become necessary. Therefore, it is difficult to hold down the area of the driving circuit.
In case of the driving circuit which includes D/A conversion circuits as mentioned above, it is difficult to hold down its area, which becomes a cause for hindering the miniaturization of semiconductor devices, particularly, active matrix liquid crystal display devices.
Further, for making semiconductor display devices highly precise and minute, the number of the pixels must be increased, that is, the number of the source signal lines must be increased. However, if the source signal lines are increased in number, then the number of the D/A conversion circuits is also increased as mentioned above, and thus, the area of the driving circuit is increased, which is a cause for impeding the realization of a high precise and minute structure.
For the reasons mentioned above, there is a growing demand for keeping small the area of an D/A conversion circuit.
Furthe

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