Sigma-delta-based frequency synthesis

Details Sigma-delta-based frequency synthesis Sigma-delta-based frequency synthesis

2001-08-29

2004-02-10

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S105000

Reexamination Certificate

active

06690215

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to frequency synthesis.
2. State of the Art
In the field of communications, it is necessary to synthesize many different frequencies, typically using a reference frequency or a small number of reference frequencies. A phase lock look (PLL) is used for this purpose.
The frequency to be synthesized and the reference frequency are not always related by integer relations. Fractional-N synthesis may be used in such instances. Originally, fractional-N synthesis (FNS) was used to refer to a technique in which an accumulator is used following a conventional divider. Upon accumulator rollover, the divider divides the signal by the next highest integer on its subsequent cycle. Hence, the divider divides the signal by N or N+1, with a duty cycle set by the accumulator. The feedback signal to the phase detector is therefore frequency modulated. A narrow PLL bandwidth averages the FM feedback to provide fractional resolution (between 1/N and 1/(N+1)). The arrangement of a typical fractional-N synthesizer is shown in
FIG. 1
, where a block
101
represents the combination divider/accumulator previously described.
More particularly, an output signal
103
of the divider/accumulator
101
is applied to a phase/frequency detector (PFD)
105
, together with a reference frequency f
ref
. The PFD produces an error signal
107
, which is filtered using a low-pass filter
109
to produce a control signal
111
for a VCO
113
. The VCO produces an output signal f
o
, which is also applied as the input signal to the divider/accumulator
101
. The elements of
FIG. 1
may be grouped into a forward path
110
and a feedback path
120
. In the arrangement of
FIG. 1
, however, discrete spurious signal components (“spurs”) are typically created in the output signal.
Fractional-N synthesis may also refer, more generally, to any non-integer frequency division. One example is the use of a sigma-delta modulator (SDM) to drive the modulus control inputs of a multi-modulus prescaler, as shown in FIG.
2
. In
FIG. 2
, a forward path
210
includes the same elements as in FIG.
1
. In the feedback path
220
, the divider/accumulator of
FIG. 1
is replaced by a multi-modulus prescaler
221
controlled by a SDM
223
. This technique also frequency modulates the feedback to the phase detector. The FM rate is much higher than in the accumulator method, so the PLL more readily averages the feedback. However, the noise component of the SDM does get through the PLL, appearing as a raised noise floor on the synthesizer output.
Both of the foregoing approaches provide finer frequency resolution than conventional integer-N PLLs, or equivalently provide lower output noise for identical resolution than integer-N PLLs. These advantages make FNS attractive. Still, the discrete spurs of the accumulator technique, or the raised noise floor of the SDM technique, leave room for improvement.
A further technique is described in U.S. Pat. Nos. 4,965,533 and 5,757,239. This technique, illustrated in
FIG. 3
, involves a direct digital synthesizer
301
followed by a PLL
303
set to a fixed multiplication ratio, multiplying the DDS output (having relatively fine frequency resolution). A typical DDS arrangement is shown in FIG.
4
. An arithmetic circuit
410
comprises an adder
401
and an N-bit accumulator
403
connected in the manner shown. In particular, an N-bit input value M and the N-bit output of the accumulator
403
are applied to the adder
401
. The adder produces an N-bit result (excluding carry bit). The accumulator
403
is updated with the adder output in accordance with F
CLK
. The output value of the accumulator
403
is used to address a ROM
405
. The ROM
405
produces a digital value which is converted to analog by a DAC
407
and low pass filtered using a LPF
409
to produce an output signal. The frequency of the output signal is that of F
CLK
scaled by the ratio M:2
N
.
Using the technique of
FIG. 3
, spurious signals in the DDS output signal are either filtered by the PLL (if outside the PLL's bandwidth) or multiplied by the PLL (if within its bandwidth). Thus, this technique is also susceptible to noise degradation.
Although not widely known, a DDS-like arrangement can be operated as a first-order SDM, as shown in FIG.
5
. An arithmetic circuit
510
is similar to the arithmetic circuit
410
of
FIG. 4
except that a carry-out signal c
o
of the adder
501
is synchronized with f
CLK
to form a signal c
o
′, which is the desired SD waveform. As compared to the conventional DDS arrangement of
FIG. 4
, the SD waveform of
FIG. 5
has a duty cycle of f
o
: f
CLK
, or M:2
N
.
In addition, a wideband frequency digitizer is described in U.S. Pat. No. 6,219,394 entitled DIGITAL FREQUENCY SAMPLING AND DISCRIMINATION issued Apr. 17, 2001 and incorporated herein by reference. As illustrated in
FIG. 6
, the wideband frequency digitizer
601
provides a sigma-delta waveform representation
603
of the frequency ratio between its input signal f
x
(
605
) and a reference F
CLK
(
607
).
Despite the foregoing techniques, a need exists for a frequency synthesis technique that simultaneously provides low noise (and low spurs) while also providing fine frequency resolution and fast switching times.
SUMMARY OF THE INVENTION
The present invention, generally speaking, satisfies the foregoing requirements using in combination within a frequency synthesis loop an SDM-based synthesizer and an SDM-based frequency digitizer. Since both blocks are SDM-based, the resulting signals can be differenced and filtered to produce a control signal for an oscillator. Low noise (and low spurs), fine frequency resolution and fast switching times may all be achieved simultaneously.


REFERENCES:
patent: 4965531 (1990-10-01), Riley
patent: 5329253 (1994-07-01), Ichihara
patent: 5604468 (1997-02-01), Gillig
patent: 6249189 (2001-06-01), Wu et al.
patent: 0 717 491 (1996-06-01), None
patent: 01/20774 (2001-03-01), None

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