Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Controlling current distribution within bath
Reexamination Certificate
2002-05-22
2004-08-10
Koehler, Robert R. (Department: 1775)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Controlling current distribution within bath
C204S232000, C204S242000, C204S272000, C204S275100, C204S280000, C204S286100, C205S123000, C205S148000, C205S157000, C205S291000, C205S292000
Reexamination Certificate
active
06773571
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to methods and apparatus for electroplating metal onto a work piece. More specifically, the invention pertains to methods and apparatus for controlling the electrical resistance and current flow characteristics in an electrolyte environment encountered by the work piece during electroplating.
BACKGROUND OF THE INVENTION
The first generation of integrated circuits that used copper as the IC level interconnecting technology was introduced by IBM in 1997. The transition from aluminum to copper required a change in process “architecture” (to damascene and dual-damascene) as well as new process technologies. Two processes used in producing copper damascene circuits are the formation of a “seed-” or “strike-” layer, which is then used as a base layer onto which copper is electroplated (“electrofill”).
A seed layer is typically a thin conductive metal (e.g. copper) film (conventionally about 1250 Å thick). The seed layer is separated from the insulating dielectric (e.g silicon oxide) by a barrier layer so that copper inlay thereon does not diffuse into the dilelectric. The seed layer carries an electrical plating current from the edge of the wafer (where electrical contact is typically made) to all trench and via structures located across the wafer surface. Ideally, the seed layer should be conformal and continuous over and into all such features and have minimal closure or “necking” at the top of the embedded features. The demand for increasingly smaller device features, there is a concomitant need for correspondingly thinner seed layers to prevent necking. It is anticipated that in the near future, seed thickness will decrease to 500 Å and may eventually decrease to as little as 100 Å.
As seed layer thickness decreases, the ability to electroplate with a high degree of uniformity becomes more problematic. One problem is the resistance of the seed layer. The use of larger wafer diameters, exacerbates this problem, because the plating current must traverse an even larger distance through the seed layer. The seed layer initially has a significant resistance radially from the edge to the center of the wafer because the seed layer is initially very thin. This resistance causes a corresponding potential drop from the edge where electrical contact is made to the center of the wafer. These effects are reported in L. A. Gochberg, “Modeling of Uniformity and 300-mm Scale-up in a Copper Electroplating Tool”,
Proceedings of the Electrochemical Society
(Fall 1999, Honolulu Hi.); and E. K. Broadbent, E. J. Mclnerney, L. C. Gochberg, and R. L. Jackson, “Experimental and Analytical Study of Seed Layer Resistance for Copper Damascene Electroplating”,
Vac. Sci. & Technol
. B17, 2584 (November/December 1999). Thus, the seed layer has a non-uniform initial potential that is more negative at the edge of the wafer. The associated deposition rate tends to be greater at the wafer edge relative to the interior of the wafer. This effect is known as the “terminal effect.” Terminal effect resistance losses are common, and they vary with time during a plating process.
Another variable that adds to the complexity of the issue is non-uniformity in the seed layer across a wafer surface. Seed layer non-uniformity imparts resistance variation across the wafer. Yet another variable is feature aspect ratio and feature density. Having a high-density of features, especially those with high aspect ratios, causes significant variation in seed layer resistance across a wafer. These issues demand improvements in hardware and processes to maintain uniform plating when thin seed layers are used to initiate electroplating. Asymmetrical shielding elements have been examined as a way to change (tailor) the composite plating process uniformity. The change in plating current was estimated as the time averaged exposure that a rotating wafer would “see” with a mask of a certain shape and size covering the part during a rotational period. This work is described in U.S. Pat. No. 6,027,631, entitled “Electroplating System with Shields for Various Thickness Profile of Deposited Layer”, by Broadbent, et al., which is herein incorporated by reference for all purposes.
Jorne et al., U.S. Pat. No. 6,132,587, describes various methods of mitigating the terminal effect. Methods to improve the uniformity of metal electroplating over the entire wafer included: increasing the resistance of the electrolyte, increasing the distance between the wafer and the anode, increasing the thickness of the seed layer, increasing the ionic resistance of a porous separator placed between the wafer and the anode, placement of a rotating distributor in front of the wafer, and establishing contacts at the center of the wafer. As well, they describe a method that uses a “rotating distributor jet” that directs varying amounts of electrolyte flow to different radii of a wafer. This method is not particularly useful because plating conditions (flow rate, replenishment of additives, etc.) vary locally and therefore create a convolution between electrofilling and uniformity. Additionally, no simple means of varying the uniformity with respect to process time is presented.
While the approaches discussed above have proven useful, they suffer a number of potential limitations. Such limitations include the inability to continuously change (throughout a plating process) the resistance compensation, the high cost of implementation, and mechanical limitations (e.g. a large number of moving part in a corrosive bath, material compatibility limitations, and reliability).
What is needed therefore, are improved apparatus and methods for uniform electroplating onto thin-metal seeded wafers, particularly wafers with large diameters (e.g. 300 mm).
SUMMARY OF THE INVENTION
The present invention pertains to methods and apparatus for electroplating a substantially uniform layer of a metal onto a work piece having a seed layer thereon. The total current of a plating cell is distributed among a plurality of anodes in the plating cell in order to tailor the current distribution in the plating electrolyte to compensate for resistance and voltage variation across a work piece due to the seed layer. Focusing elements are used to create “virtual anodes” in proximity to the plating surface of the work piece to further control the current distribution in the electrolyte during plating.
One aspect of the invention is a method for electroplating a substantially uniform layer of a metal onto a work piece having a seed layer thereon. Such methods may be characterized by the following operations: (a) immersing at least that portion of the work piece having the seed layer thereon in an electrolyte, the electrolyte containing ions of the metal; and (b) passing a current between the seed layer and a plurality of anodes whereby the current is distributed among the plurality of anodes such that, for any instance in time during plating, the metal is deposited substantially uniformly onto the entire surface area of the seed layer.
Semiconductor wafers are one such work piece. Preferably the entire surface area of the seed layer consists of an inner and an outer region. In one example, the inner region is a circular surface area, the center of the circular surface area coincident with the center of the wafer. The outer region is an annular surface area defined by an outer circle, substantially coincident with the outermost edge of the wafer, and an inner circle of the same diameter as the inner region. Preferably, the inner region includes between about 15 and 25 percent of the surface area of the seed layer, the outer region covering the remainder of the surface area of the seed layer.
In one example, distributing the current between a plurality of anodes means distributing the current between an inner anode, proximate to the inner region, and an outer anode, proximate to the outer region. For example, when electroplating metal onto a wafer with a thin seed layer (where electrical contact is made at the wafer edge), the plating cur
Blackman Brian Paul
Mayer Steven T.
Patton Evan E.
Perry Harold D.
Ponnuswamy Thomas Anand
Beyer Weaver & Thomas LLP
Koehler Robert R.
Novellus Systems Inc.
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