Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state
Reexamination Certificate
2003-02-20
2004-06-29
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to nonconductive state
C438S601000, C257S529000
Reexamination Certificate
active
06756256
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the priority benefit of Taiwan application serial no. 91103526, filed on Feb. 27, 2002.
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention is generally related to a method for preventing a burnt fuse pad from further electrical connection, and more particularly to a fabrication method of a bump on a wafer to prevent a burnt fuse pad from further electrical connection.
2. Description of Related Art
Semiconductor devices are usually provided with a fuse system which provides alternative electrical routing depending on whether the fuse wire is burnt or not. Using semiconductor devices as an example, in the fabrication of semiconductor components such as DRAM or SDRAM, due to the high integration of memory cells defects cells are commonly found. As the integration level is continuously increasing, the production yield of these semiconductor devices is lowered. Therefore in order to increase the yield of the fabrication of semiconductor devices, prior art utilizes redundancy circuit technology to improve the yield of the fabrication of semiconductor devices.
In the fabrication process of semiconductor components, besides the main memory cell array that is originally used for storing two bit data, a redundancy memory cell array is additionally fabricated in the peripheral region of the main memory cell array for replacing the defect memory cells during the fabrication process. The main memory cell array and the redundancy memory array are connected via the fuse pads. Therefore when a defect memory cell is being recovered, laser will burn the central region of the fuse pad to allow the redundancy memory cell array to replace the main memory cell array. Oppositely if no defect memory cell recovery is required, no laser burning is applied to the central region of the fuse pad.
After the memory chip is tested and recovered, the chip must undergo a packaging process. Prior art provides a kind of memory chip packaging such as small out-line package (SOP) which first adheres a memory chip onto a leadframe and then by means of wire bonding electrically connects the bonding pads of the chip and one end of the inner leads by conductive wires. Afterwards, a molding compound is deposited to encapsulate the chip, the conductive wires, and a part of the leadframe. The memory chip uses the outer lead which are located outside the leadframe as the signal input and output terminal. It is to be noted that when the memory chip is being recovered, a gap that is created by the laser burning the central region of the fuse pads is entirely filled up by the molding material during the packaging process.
In order for these chips with fuse pads to work with flip chip (F/C) packaging method, bumps must be formed on the bump pads of the chip and they must be connected to a substrate via a carrier. It is to be noted that before forming bumps on the bumps pads of the chip, an under ball metallurgy (UBM) layer is usually first formed on the bump pads by either evaporation, sputtering, or electroplating to increase the connectivity between the bumps and the bump pads. Furthermore in the process of forming UBM layer, a part of the conductive material is still left over inside the gaps of the burnt fuse pads which cause electrical conductivity of originally burnt fuse pads. As a result, the original chip after recovery process loses its effect.
SUMMARY OF INVENTION
The present invention provides a method for preventing the burnt fuse pads from further electrical connection, which is suitable in the process of bumps on the bumps pads of a wafer. An insulating material is deposited into the gap caused by the burnt fuse pads. This results in that the burnt fuse pads on the two sides of the gap are electrically insulated to retain the effect of the original chip recovery process and to allow bumps to be formed on the bump pads of the wafer.
To fulfill the aforementioned object, the present invention provides a method for preventing burnt fuse pads from further electrical connection, which is suitable for the bump fabrication process for forming at least a bump on a wafer. A wafer with an active surface, a passivation layer, at least a bump pad and at least a fuse pad are provided. The bump pads and the fuse pads are located on the active surface of the wafer and the passivation layer exposes the bump pads and the fuse pads, wherein the central region of the fuse pads is burnt creating a gap. The present invention provides a method for preventing burnt fuse pads from further electrical connection which forms a dielectric layer on the active surface of the wafer that covers the bump pads and the fuse pads. A part of the material from the dielectric layer fills up the gaps in the fuse pads, and following the dielectric layer is patterned but retaining the dielectric layer that is covering the fuse pads and removing part of the dielectric layer that is covering the bump pads for exposing the bump pads. Therefore afterwards when forming the UBM layer on the bump pads of the wafer, the material from the UBM layer will not bridge the burnt fuse pads on two sides of the gap or will not fill up the gap which retains an electrical insulation status.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6566730 (2003-05-01), Giust et al.
patent: 6664142 (2003-12-01), Liu
patent: 6667195 (2003-12-01), Liu
patent: 2003/0027379 (2003-02-01), Liu
Wolf et al. Silicon Processing for the VLSI Era, vol. 1—Process Technology, pp. 428, 529-534, 539-542, and 555, Lattice Press, 1986.
Chen Jau-Shoung
Chou Yu-Chen
Fang Jen-Kuang
Huang Min-Lung
Lee Chun-Chi
Advanced Semiconductor Engineering Inc.
Jiang Chyun IP Office
Kennedy Jennifer M.
Niebling John F.
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