Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-07-15
2004-11-09
Lam, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185210, C365S185220
Reexamination Certificate
active
06816413
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2002-206177, filed Jul. 15, 2002; and No. 2003-193728, filed Jul. 8, 2003, the entire contents of both of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory. More specifically, the invention relates to a multilevel flash memory wherein a multi-level of three or more levels is stored in a single cell.
2. Description of the Related Art
A binary flash memory for storing two data items of different levels (referred to as binary data hereinafter) widely spreads as a nonvolatile semiconductor memory.
FIG. 16
shows the arrangement of the main part of a binary flash memory (e.g., a NOR type). Referring to
FIG. 16
, a cell array
101
includes a plurality of memory cells (main cells) MC arranged in matrix. The control gates of memory cells MC arranged in one row are connected to a common one of a plurality of word lines WL
0
to WLn. The drain regions of memory cells MC arranged in one column are connected to a common one of a plurality of bit lines BL
0
to BLk. Generally, the cell array
101
is divided into a plurality of blocks. The source regions of memory cells MC in one block are connected to a common one of a plurality of source lines (not shown). The bit lines BL
0
to BLk are connected to a sense amplifier
102
through their corresponding one of a plurality of select transistors ST
0
to STk. A plurality of column lines COL
0
to COLm are connected to the gates of the select transistors ST
0
to STk, respectively.
A reference circuit
103
includes one reference cell RC and a plurality of dummy cells DC. The drain regions of the reference cell RC and dummy cells DC are connected to each other. The control gate of the reference cell RC is connected to a reference word line RWL. The drain region of the reference cell RC is connected to the sense amplifier
102
via an n-type MOS transistor
103
a
. A reference column line RCOL is connected to the gate of the transistor
103
a.
The sense amplifier
102
includes n-type MOS transistors
102
a
and
102
b
, p-type MOS transistors
102
c
and
102
d
and a differential amplifier
102
e
. The source region of the n-type MOS transistor
102
a
is connected to the drain regions of the select transistors ST
0
to STk in the cell array
101
. The drain region of the n-type MOS transistor
102
a
is connected to the gate and the drain region of the p-type MOS transistor
102
c
and the inverted input terminal of the differential amplifier
102
e
. On the other hand, the source region of the n-type MOS transistor
102
b
is connected to the drain region of the n-type MOS transistor
103
a
in the reference circuit
103
. The drain region of the n-type MOS transistor
102
b
is connected to the gate and the drain region of the p-type MOS transistor
102
d
and the noninverted input terminal of the differential amplifier
102
e
. The differential amplifier
102
e
outputs sensed cell data (Dout) from its output terminal.
A BIAS power supply voltage is applied to the gate of each of the n-type MOS transistors
102
a
and
102
b
. A power supply voltage Vcc is applied to the source region of each of the p-type MOS transistors
102
c
and
102
d.
FIG. 17
shows the characteristics of the binary flash memory with the above arrangement. More specifically,
FIG. 12
shows a relationship (Vg-Icell (Id) characteristics) between a gate voltage Vg applied to the control gate and a cell current Icell (drain current Id) per load current in both the memory cell MC and the reference cell RC. In data read and program verify modes, a read voltage Vr is applied to the control gate of the reference cell RC. Thus, the sense amplifier
102
always determines the cell current Icell (“0” or “1”) by the reference current Iref.
In the Vg-Id characteristics of the memory cell MC, the state of a relatively large number of electrons stored in a floating gate (or a high threshold voltage Vth of the memory cell MC) is considered to be data “0”. The memory cell MC that stores the data “0” is referred to as a “0” cell. Conversely, the state of a relatively small number of electrons (or a low threshold voltage Vth of the memory cell MC) is considered to be data “1”. The memory cell MC that stores the data “1” is referred to as a “1” cell.
The cell current of the reference cell RC (reference current Iref) is set to approximately half the cell current Icell of the memory cell MC. In other words, when the gate voltage Vg is equal to the read voltage Vr, a difference between the cell current Icell of the memory cell MC and the cell current Iref of the reference cell RC in the “0” cell and that in the “1” cell are almost equal to each other.
FIG. 18
shows a correlation between the gate voltage (Vg-hontai) of the memory cell MC and the gate voltage (Vg-ref) of the reference cell RC in each of operating modes. For example, in program verify (PV) mode for defining a data program state “0”, a program verify voltage Vpv (=6.5V) is applied to the control gate of the memory cell MC. A difference between the program verify voltage Vpv and the read voltage Vr (=5.5V) that is applied to the control gate of the reference cell RC is reflected in the threshold voltage Vth of the memory cell MC. Thus, the “0” cell is usually cut off when the gate voltage Vg is equal to the read voltage Vr. Similarly, for example, in erase verify mode (EV) mode for defining a data erase state “1”, an erase verify voltage Vev (=4V) is applied to the control gate of the memory cell MC. If the erase verify voltage Vev is set at roughly the same as the reference voltage Vtref, the current flowing when the gate voltage Vg of the “1” cell is equal to the read voltage Vr, i.e., the cell current Icell becomes almost equal to 2Iref.
In other words, the sense amplifier
102
senses a current difference (+Iref/−Iref) between the cell current Icell of the memory cell MC and the cell current Iref of the reference cell RC, which is caused when the gate voltage Vg is equal to the read voltage Vr and converts it into a digital signal of “0” or “1”. Accordingly, cell data is read out.
FIG. 19
shows the distribution of threshold voltages Vth with respect to the gate voltage Vg in the memory cell (binary cell) MC capable of storing binary data “0” and “1”. For example, in over-erase verify (OEV) mode for compensating for the lower limit of the cell distribution corresponding to the data erase state “1”, an over-erase verify voltage Voev (=2V), which is lower than the erase verify voltage Vev, is applied to the control gate of the memory cell MC. A cell that becomes “1” when the over-erase verify voltage Voev is applied is detected. Data is written such that the threshold voltage Vth of a bit corresponding to the cell becomes “0” when the over-erase verify voltage Voev is applied. Thus, the cell distribution corresponding to the erase state “1” falls within a given range.
The cell area per bit is a cost index of a flash memory. There is a multilevel flash memory that can be reduced in cost by storing data of a plurality of bits in one cell as well as by decreasing the cell area. A four-level flash memory for storing four levels or four data items of different levels (four-level data) has been already reported in, for example, M. bauer et al., “A Multilevel-Cell 32Mb Flash Memory”, ISSCC Digest of Technical Papers, pp. 132-133, 1995.
The cell distribution of the four-level flash memory is discrete with respect to the gate voltage. More specifically, in verify mode, a margin for reading is secured by varying the gate voltage of a memory cell as in the binary flash memory. On the other hand, cell data is read out at a constant gate voltage.
Assuming that the memory cells vary in transconductance or the ratio of a change in cell current to that in gate voltage varies, a margin (read margin) for the reference current of re
Kabushiki Kaishi Toshiba
Lam David
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