Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2000-02-25
2004-08-31
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
Reexamination Certificate
active
06785799
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multiprocessor used in an information processing device, which performs pipeline processing of instructions, and a method for controlling the multiprocessor.
2. Description of the Related Art
In a conventional method for improving performance of a microcomputer, a plurality of processors are mounted on the same semiconductor chip, and the processors operate in parallel to one another. According to this method, when the processing capacity of a single processor is insufficient for implementing a desired application, operations of the application are allocated to a plurality of processors, thereby realizing the implementation of the application. Another application example of this method is a memory-shared multiprocessor in which a plurality of processors share a single memory. In the memory-shared multiprocessor, instructions and/or data can be shared between the plurality of processors.
Although the memory-shared multiprocessor has an advantage of sharing the instructions and the data between the processors, the memory-shared multiprocessor also has a disadvantage such that a conflict occurs when the plurality of processors simultaneously access the shared memory. In order to remove such a conflict, arbitration between the memory accesses is required, whereby the memory accesses of the processors have to be on standby during an arbitration period.
Furthermore, the order of the memory accesses of the processors depends on the content of data processed by the application. In the case where the application processes various data, it is impossible to predict the order of the memory accesses. Thus, a standby period of each processor before accessing the memory, which is caused by the arbitration between the memory accesses, cannot be estimated, whereby it is difficult to estimate the run duration of the application.
As described above, in the conventional memory-shared multiprocessor, the run duration of the application cannot be estimated because of the arbitration of a conflict between the memory accesses. Thus, it is difficult to apply the conventional memory-shared multiprocessor to the communication DSPs (digital signal processors) that requires real-time processing, or the like.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a multiprocessor includes M banks storing a plurality of instructions; and N processors each having N instruction fetch stages, wherein each of the N processors processes one of the plurality of instructions in a pipelined manner, where N is an integer equal to or greater than 2, and M is an integer equal to or greater than N, wherein each of the N processors fetches one of the plurality of instructions at a different instruction fetch stage from instruction fetch stages used by other processors.
In one embodiment of the present invention, each of the N processors fetches one of the plurality of instructions at one of the N instruction fetch stages, and processes the instruction in a pipelined manner, thereby outputting an address.
In another embodiment of the present invention, the multiprocessor further includes an address select section for outputting a bank address based on the address output from the each of the N processors.
Instill another embodiment of the present invention, each of the M banks outputs one of the plurality of instructions that corresponds to the bank address output from the address select section.
Instill another embodiment of the present invention, when the fetched instruction is a branch instruction, after the branch instruction is processed, the processor changes the instruction fetch stage at which the instruction is fetched from one to another.
In still another embodiment of the present invention, each of the N processors includes an instruction register section that receives one of the plurality of the instructions, a bank select signal, a fetch stage select signal, and an NOP select signal to output an instruction code; a decoder section that receives the instruction code to output a branch instruction signal and a branch address; a control section that receives the branch instruction signal, the branch address, and an instruction pointer signal to output the fetch stage select signal, the NOP select signal, and an address branch signal; and an instruction pointer section that receives the fetch stage select signal, the address branch signal, and the branch address to output the bank select signal, the instruction pointer signal, and the address.
According to another aspect of the present invention, in a multiprocessor including M banks storing a plurality of instructions, N processors wherein each of the N processors has N instruction fetch stages and processes one of the plurality of instructions in a pipelined manner, where N is an integer greater than 2, and M is an integer greater than N, and an address select section, a method for controlling the multiprocessor includes a step at which each of the N processors fetches one of the plurality of instructions at at least one of the N instruction fetch stages; a step at which the each of the N processors processes the fetched instruction to output an address; a step at which the address select section outputs a bank address to one of the M banks based on the address from the each of the plurality of the N processors; and a step at which the one of the M banks outputs one of the plurality of instructions that correspond to the bank address, wherein each of the N processors fetches one of the plurality of instructions at an instruction fetch stage different from the instruction fetch stages used by other processors.
In one embodiment of the present invention, when the fetched instruction is a branch instruction, after the branch instruction is processed, the processor changes the instruction fetch stage at which the instruction is fetched from one to another.
Thus, the invention described herein makes possible the advantages of (1) removing the necessity for arbitration between memory accesses when a conflict occurs in a memory-shared multiprocessor, thereby omitting an arbitration circuit for memory accesses from the multiprocessor, and (2) providing a memory-shared multiprocessor in which a run duration of an application can be easily estimated.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.
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Ueda Katsuhiko
Yamasaki Masayuki
Chan Eddie
Li Aimee J.
Snell & Wilmer LLP
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