Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2003-02-21
2004-08-10
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S291000, C257S292000, C257S443000, C257S446000, C257S461000
Reexamination Certificate
active
06774453
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, a photoelectric conversion device, an amplification type solid state image pickup device using the same, and a system using the same. In particular, the present invention relates to an image pickup device such as a digital camera, a video camera, a copying machine, or a facsimile and a system therefor.
2. Related Background Art
A large number of image sensors, each of which has solid state image pickup elements including a photoelectric conversion element arranged in one-dimension or two-dimension, are mounted in a digital camera, a video camera, a copying machine, a facsimile, or the like. Examples of the solid state image pickup element include a CCD image pickup element and an amplification type solid state image pickup element.
These image pickup elements tend to increase the number of pixels formed therein. In addition, a photo diode area is accordingly reduced as an area of a pixel decreases. Thus, the need for treating the smaller amount of signal charge and the need for minimizing a leak current of a photo diode resulting from a noise component arise.
A circuit structural example of an amplification type solid state image pickup element is shown in FIG.
15
. In the amplification type solid state image pickup element, a unit pixel has at least a photo diode PD and a transistor Tr for amplifying a photo signal stored in the photo diode. The pixel structure is the same as in a pixel structure shown in
FIG. 3
as described later. Signal readout and reset operations of respective pixels to a pixel row are controlled by a vertical scanning circuit (VSR). The read signals are stored in capacitors C and outputted for each pixel column in succession from a horizontal output line by a horizontal scanning circuit (HSR).
FIG. 16
shows a sectional structure of a photo diode in a unit cell of a conventional amplification type MOS sensor. As shown in
FIG. 16
, an n-type region
103
composing a photo diode together with a p-type semiconductor layer
102
on an n-type substrate
101
is formed in a self-aligning manner with a selective oxide layer
104
as an element isolation layer. Thus, it is constructed such that an area of the n-type region
103
corresponding to an area of the photo diode is increased to a limit. A P+ type channel stop region
106
for improving a punch-through withstand voltage between a source drain region
107
of an adjacent MOS transistor and the n-type region
103
of the photo diode is formed under the selective oxide layer
104
. In addition, a wiring layer
105
of a transistor is formed on the selective oxide layer
104
.
However, in
FIG. 16
, when a potential of the wiring layer
105
of the transistor is set to a HIGH level (for example, +5 V), an effective concentration of the p+ type channel stop region
106
located thereunder is reduced and a minority carrier concentration in a region under the wiring layer
105
is increased. When the minority carrier (electron) is diffused into the photo diode, a dark current of the photo diode is increased.
For measures against this, it is considered that the concentration of the P+ type channel stop region is increased. However, a junction withstand voltage with an N++ region of the adjacent source drain region
107
is reduced or an interjunction leak current is increased.
On the other hand, it is considered that the selective oxide layer
104
is made thick. However, when it is made thick, a step of the wiring layer
105
becomes larger. Thus, there is the case where disconnection or short circuit is easy to cause. Therefore, it is inconvenience for the formation of minute wiring.
Accordingly, there is a problem in that a noise is increased by the increase of a dark current so that the deterioration of S/N ratio is caused.
SUMMARY OF THE INVENTION
In order to solve the above-mentioned problem, a semiconductor device according to the present invention includes: a semiconductor element having a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type which is formed in the first semiconductor region; an element isolation layer formed between the semiconductor element and an adjacent element; a third semiconductor region of the first conductivity type having a higher concentration than the first semiconductor region formed under the element isolation layer; and a conductor layer formed on a portion of the element isolation layer, in which a fourth semiconductor region of the first conductivity type having a higher concentration than the third semiconductor region is further provided in at least a portion of a region opposite to the conductor layer through the element isolation layer sandwiched therebetween.
Further, a photoelectric conversion device according to the present invention includes: a photoelectric conversion element having a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type which is formed in the first semiconductor region; an element isolation layer formed between the photoelectric conversion element and an adjacent element; a third semiconductor region of the first conductivity type having a higher concentration than the first semiconductor region formed under the element isolation layer; and a conductor layer formed on a portion of the element isolation layer, in which a fourth semiconductor region of the first conductivity type having a higher concentration than the third semiconductor region is further provided in at least a portion of a region opposite to the conductor layer through the element isolation layer sandwiched therebetween.
REFERENCES:
patent: 6281533 (2001-08-01), Miyagawa et al.
patent: 6423993 (2002-07-01), Suzuki
patent: 10-98176 (1998-04-01), None
Canon Kabushiki Kaisha
Fitzpatrick ,Cella, Harper & Scinto
Wojciechowicz Edward
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