Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-05-24
2004-11-30
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185110, C365S185160, C365S185330
Reexamination Certificate
active
06826080
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory, and more particularly to a nonvolatile virtual ground memory array and method of operation thereof to avoid cell disturb.
2. Description of the Related Art
Nonvolatile memory retains stored data when power is removed, which is required or at least highly desirable in many different types of computers and other electronic devices. Nonvolatile semiconductor memory devices are generally divided into two main classes. The first class is based on the storage of charge in discrete trapping centers of a dielectric layer of the structure. The second class is based on the storage of charge on a conducting or semiconducting layer that is completely surrounded by a dielectric, typically an oxide.
A common type of stored charge device is the stacked gate transistor, also known as a floating gate transistor, in which cell programming is performed through channel hot-electron injection (“CHE”). An illustrative self-aligned double-polysilicon stacked gate structure
1
is shown in
FIG. 1. A
floating gate
14
, typically a doped polysilicon layer, is sandwiched between two insulator layers
12
and
16
, typically oxide. The top layer of the stack is a control gate electrode
10
, typically a doped polysilicon layer, to which a control gate voltage V
G
may be applied. The stacked gate structure is shown symmetrically overlying a heavily doped n+ source region
20
and a heavily doped n+ drain region
22
, to which a source voltage V
S
and a drain voltage V
D
respectively may be applied, as well as a channel region between the source region
20
and the drain region
22
. The channel region is part of a p-well
28
, which also contains the source region
20
, the drain region
22
, and a heavily p+ doped contact region
24
to which a p-well bias voltage P
D
may be applied. The p-well
28
is contained within an n-well
30
, which also contains a heavily n+ doped contact region
26
to which an n-well bias voltage V
N
may be applied. The n-well
30
is in turn contained in the p-type substrate
32
. When high voltages are applied simultaneously to the both the drain
22
and the gate
10
of cell of
FIG. 1
, the high voltage across the drain-to-source produces a high channel current and channel field that generate hot electrons in a pinch off region near the drain
22
(as indicated by wedge-shaped region and the notation e-). The high voltage on the control gate
10
couples a voltage to the floating gate
14
that attracts the hot electrons, effectively injecting them into the floating gate (as indicated by the upward-turned arrows adjacent the e-notation).
A technique is known that uses negative substrate biasing of the flash memory cells to overcome some of the disadvantages of conventional CHE. An example of this technique is disclosed in U.S. Pat. No. 5,659,504 issued Aug. 19, 1997 (Bude et al., “Method and Apparatus for Hot Carrier Injection”). The Bude et al. programming technique, which is referred to as channel-initiated secondary electron injection (“CISEI”), uses a positive bias voltage of about 1.1 volts to about 3.3 volts at the drain and a negative bias voltage of about −0.5 volts or more negative at the substrate, with the source at zero volts. The source-drain voltage causes some channel hot electron generation while the substrate bias promotes the generation of a sufficient amount of secondary hot electrons having a sufficient amount of energy to overcome the energy barrier between the substrate and the floating gate. The secondary hot electrons are primarily involved in charging the floating gate. The programming of the flash memory array using CISEI transistors is relatively quickly achieved with low programming current, low drain voltage, and smaller cell size (shorter channel length) relative to flash memory arrays using CHE transistors. However, simultaneous multiple byte programming and page mode programming are still difficult to achieve. Unfortunately, as in the case the CHE memory array, the use of isolating select transistors in CISEI memory cells increases their size, and the technique of repeated programming groups of bits until the desired amount of memory is programmed can cause program-disturb.
Self-aligned double-polysilicon stacked gate structures such as the structure
1
shown in
FIG. 1
have been used in various contactless virtual ground configurations to achieve high memory density levels.
FIG. 2
is a schematic diagram showing a basic virtual ground array architecture
200
that uses a cross-point array configuration of memory cells interconnected by row lines and column lines. Word lines are shown in
FIG. 2
as extending from an X decoder
206
into respective sectors of the array, represented by sectors
210
,
211
,
212
,
213
,
214
and
215
. One example of a type of row line is the WSi
2
/Poly control gate word line. Column lines are shown in
FIG. 2
as extending between a program column select
204
and a read column select
208
, both of which receive a decoded y-address from a Y decoder
202
. Column lines are formed in a variety of ways. A column line may be formed of highly conductive material, such as the word line. However, one type of column line in common use in virtual ground arrays is the continuous buried n+ diffusion that forms a sub-bit line of the memory array. Metal (not shown) typically is used to make contact to the buried sub-bit line periodically, for example every sixteenth word line, to reduce bit line resistance. Due to elimination of the common ground line and the drain contact in each memory cell, extremely small cell size is realized. A great many virtual ground array architectures and nonvolatile semiconductor memory devices have been developed, as exemplified by the following patents: U.S. Pat. No. 6,175,519 issued Jan. 16, 2001 to Liu et al.; U.S. Pat. No. 5,959,892 issued Sep. 28, 1999 to Lin et al.; U.S. Pat. No. 5,646,886 issued Jul. 8, 1997 to Brahmbhatt; and U.S. Pat. No. 5,060,195 issued Oct. 22, 1991 to Gill et al.
Programming, erasing and reading of the memory cells in a virtual ground memory array is obtained by the use of suitable source and drain decoding. Several illustrative sectors
210
-
215
are shown in
FIG. 2
, each of which typically contains about 512 bytes or 4096 stacked gate transistors, as well as some redundant bytes, but which may contain more or less as desired. Unfortunately, source and drain decoding circuits tend to be extremely complex because of both the need to use a counterbiasing scheme to reduce voltage disturb on cells sharing the same bit line cell and on cells on other word lines, as well as the large number of decoding combinations necessary for a typical sector of memory.
Programming, erasing and reading of the memory cells may be simplified somewhat by the use of asymmetrical floating gate transistors. Examples of one type of asymmetrical floating gate transistor and of a virtual ground memory array incorporating it are disclosed in U.S. Pat. No. 5,418,741, issued May 23, 1995 to Gill. Each shared column line has two junctions for each pair of memory transistors that share the column line. One junction is graded for source regions and the other is graded for drain regions. The deep source regions are graded, i.e. gradually sloped, to minimize programming at the source junction region, while the relatively shallow drain regions are abrupt, i.e. steeply sloped, to improve the injection efficiency of the device. The bit line is formed by the shallow drain region implant, which is an n+ implant. Due to the different junction characteristics of adjacent cells, the programming of one cell is said not to disturb the state of the immediately adjacent cell.
Even with the use of asymmetrical floating gate transistors, the programming of cells in the array using CHE and CISEI requires careful biasing schemes on the bit lines to reduce the disturb voltage on an adjacent cell sharing the same bit line. Generally, CHE programming of
Han Kyung Joon
Kwon Gyu-Wan
Lee Jong Seuk
Park Joo Weon
Altera Law Group LLC
NexFlash Technologies, Inc.
Phan Trong
LandOfFree
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