Amplifiers – With periodic switching input-output
Reexamination Certificate
2003-06-06
2004-11-02
Nguyen, Patricia (Department: 2817)
Amplifiers
With periodic switching input-output
C330S258000, C330S260000, C330S051000
Reexamination Certificate
active
06812784
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to switched-capacitor systems and, more particularly, to differential amplifiers in such systems.
2. Description of the Related Art
FIG. 1
illustrates a switched-capacitor system
20
in which a sample capacitor C
s
has a top plate
21
coupled to the inverting input of a differential amplifier
22
and a bottom plate
23
coupled through an input sample switch
24
to an input port
25
. The differential amplifier
22
drives an output port
26
and a transfer capacitor C
t
is coupled across the differential amplifier. The differential amplifier has a high gain so that its non-inverting input has substantially the same potential as its inverting input. Finally, a second sample switch
27
and a transfer switch
28
are respectively coupled to the top and bottom plates
21
and
23
.
In an operational sample mode, the input and second sample switches
24
and
27
are closed so that an analog input signal S
in
at the input port
25
urges a sample charge Q
s
into the sample capacitor C
s
to thereby acquire a sample signal S
s
=Q
s
/C
s
across the sample capacitor. In an operational transfer mode, the first and second sample switches
24
and
27
are opened and the transfer switch
28
is closed to transfer the sample charge Q
s
into the transfer capacitor C
t
and thus generate an output signal S
out
=Q
s
/C
t
at the output port
26
.
The switched-capacitor system
20
of
FIG. 1
is thus formed with the differential amplifier
22
and a switched-capacitor structure
29
that includes the sample and transfer capacitors C
s
and C
t
. The switched-capacitor structure
29
acquires a sample signal S
s
in a sample mode and the differential amplifier processes the sample signal S
s
into the output signal S
out
across the output capacitor during the transfer mode. A transfer function of C
s
/C
t
is thus realized and this transfer function is represented in the graph
30
of
FIG. 2
by a plot
32
which has a slope of C
s
/C
t
.
The switched-capacitor system
20
(and differential versions thereof) is especially suited for use as a sampler in a variety of signal conditioning systems (e.g., pipelined analog-to-digital converters (ADCs)). In such systems, the switches of the system
20
of
FIG. 1
are typically realized with complementary metal-oxide-semiconductor (CMOS) transistors. This realization is exemplified in
FIG. 1
by a CMOS transistor
34
that is substituted for the input sample switch
24
as indicated by the substitution arrow
35
.
In pipelined ADCs, an initial ADC stage (e.g., a flash ADC) typically converts an analog input signal into at least one most-significant bit Do of a digital output signal that corresponds to the input signal S
in
. At the same time, the sampled signal is processed into a residue signal S
res
that is suitable for subsequent processing by downstream ADC stages into the less-significant bits of the output digital signal.
If the initial ADC stage is a 1.5 bit converter stage, for example, it provides a residue signal S
res
that corresponds to the plot
36
in
FIG. 2
which has two steps
37
that are equally spaced from the midpoint of the range of the input signal S
in
. The steps are initiated by decision signals from the initial ADC stage. The plot
36
of the residue signal S
res
, therefore, has three segments defined by the steps
37
and each segment has a slope that is twice the slope of the plot
32
.
The residue signal illustrated by the plot
36
can be generated, for example, by supplementing the sample capacitor C
s
of
FIG. 1
with an additional sample capacitor to realize the increased slope (i.e., increased gain) and by replacing the transfer switch
28
with a multipole transfer switch
38
as indicated by the substitution arrow
39
. The transfer switch responds to digital decision signals S
dgtl
from the initial ADC stage by applying selected offset signals (e.g., +V and −V) to the bottom plate of at least one of the sample capacitors and the offset signals generate the steps
37
in the plot
32
of FIG.
2
. When the switched-capacitor system
20
of
FIG. 1
is modified in this fashion, it is typically referred to as a multiplying digital-to-analog converter (MDAC).
The speed and accuracy of the sample and transfer modes of the switched-capacitor system
20
are strongly dependent upon the processing performance of the differential amplifier
22
. Because the system
20
operates in sample and transfer modes, the differential amplifier must function in a demanding noncontinuous operation which often compromises its performance.
BRIEF SUMMARY OF THE INVENTION
The present invention is directed to improved differential amplifiers for use with switched-capacitor structures. Amplifier embodiments of the invention include a differential pair of high-transconductance transistors for generation of differential currents and route common-mode feedback signals along an independent path so that sufficient headroom is provided for other high-transconductance transistors that generate common-mode currents. The differential and common-mode currents preferably generate differential and common-mode output signals in finite output impedances of active loads.
The novel features of the invention are set forth with particularity in the appended claims. The invention will be best understood from the following description when read in conjunction with the accompanying drawings.
REFERENCES:
patent: 3982196 (1976-09-01), Poujois
patent: 5180932 (1993-01-01), Bengel
patent: 5414311 (1995-05-01), Carley
patent: 5942942 (1999-08-01), Wang
patent: 5977894 (1999-11-01), McCarroll et al.
patent: 6127948 (2000-10-01), Hillis et al.
Kuppel, Jacobs, Patrick & Heybl
Nguyen Patricia
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