Method and apparatus for interrupt management for low power PDA

Details Method and apparatus for interrupt management for low power PDA Method and apparatus for interrupt management for low power PDA

1994-09-30

1998-01-13

Harvey, Jack B.

395735, 395726, 395673, G06F 1324, G06F 1326

Patent

active

057088160

ABSTRACT:
A method and system for operating a computer system in a low power mode in which the central processor unit (CPU) responds only to system events that require CPU operation is described. The invention inclues providing register banks on system logic coupled to the CPU which determines whether interrupt signals generated on the system require CPU attention and the priority to be accorded to the processes associated with the interrupt signals.

REFERENCES:
patent: 5148544 (1992-09-01), Cutler et al.
patent: 5361392 (1994-11-01), Fourcroy et al.
patent: 5414839 (1995-05-01), Joshi

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