Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-03-12
2004-06-29
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S063000, C365S230030
Reexamination Certificate
active
06757197
ABSTRACT:
Japanese Patent Application No. 2002-77857, filed on Mar. 20, 2002, is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a file storage type non-volatile semiconductor memory device including memory cells, each of the memory cells having two non-volatile memory elements controlled by one word gate and two control gates.
As one type of non-volatile semiconductor memory device, a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor or -Substrate) non-volatile semiconductor memory device is known. In the MONOS non-volatile semiconductor memory device, a gate insulating layer between a channel and a gate is formed by stacking a silicon oxide film, silicon nitride film, and silicon oxide film, and charges are trapped in the silicon nitride film.
The MONOS non-volatile semiconductor memory device is disclosed by Y. Hayashi, et al, in 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123. This literature discloses a twin MONOS flash memory cell including two non-volatile memory elements (MONOS memory elements or cells) controlled by one word gate and two control gates. Specifically, one flash memory cell has two charge trap sites.
A memory cell array region is formed by arranging a plurality of twin MONOS flash memory cells having such a structure in a row direction and a column direction.
Two bit lines, one word line, and two control gate lines are connected with the twin MONOS flash memory cell.
The operations of this type of flash memory include erasing, programming, and reading of data. Data is programmed in or read from a plurality of bits of selected cells (selected non-volatile memory elements) at the same time. Each bit signal is input or output through an I/O line.
Therefore, each of the bit lines connected with each of an arbitrary number of memory cells is connected in common with one I/O terminal through pass gate circuits. One bit line is connected with one I/O terminal through one of the pass gate circuits. Data is read or programmed in a unit of 8 bits or 16 bits by performing the read or program operation for a plurality of I/O terminals at the same time, for example.
BRIEF SUMMARY OF THE INVENTION
The present invention may provide a file storage type non-volatile semiconductor memory device suitable for simultaneously reading data from memory cells or programming data to memory cells, the number of bits of the data being greater than the number of I/O terminals.
According to the present invention, there is provided a file storage type non-volatile semiconductor memory device comprising:
a memory cell array region including a plurality of memory cells arranged in a column direction and a row direction, each of the memory cells having first and second non-volatile memory elements that are controlled by one word gate and first and second control gates;
a plurality of sector regions obtained by dividing the memory cell array region in the column direction;
a plurality of control gate driver sections each of which is provided for each of the sector regions;
four main control gate lines extending in the row direction in each of the sector regions; and
a plurality of sub control gate lines extending in the column direction in each of the sector regions, and each of the sub control gate lines connecting the first and second control gates which are adjacent to each other in the row direction and belonged to different two of the memory cells which are adjacent to each other in the row direction,
wherein the sub control gate lines are sequentially connected to one of the four main control gate lines in the row direction, in each of the sector regions.
In this configuration, the memory cells belonging to the same row in one sector are selected by potential setting of the word gate. Selection of the cells in the column direction is performed by setting a potential corresponding to a mode such as a read or program mode to each of the four sub control gate lines adjacent to one another in the row direction through the four main control gate lines in one sector region driven by one of the control gate driver sections.
The reason why there are four main control gate lines is because the minimum number of memory cells necessary for driving one cell when addressing in a binary system is four. So that one of each four memory cells adjacent in the row direction among the memory cells in the same row is selected. Therefore, this configuration is advantageous for reading from or programming in a number of cells at the same time. Moreover, since each of the main and sub control gate lines is independent in a corresponding sector, occurrence of disturbance in the non-selected cells in the sector regions other than the sector region including the selected cell can be prevented when programming or erasing data.
In each of the sector regions, all the sub control gate lines are directly connected with the four main control gate lines, and there is no control-gate select gate. It is unnecessary to provide the control-gate select gate and a driver for driving the control-gate select gate, so that the mounting area is saved and mounting at high density can be implemented.
This file storage type non-volatile semiconductor memory device may further comprise:
a plurality of main bit lines extending in the column direction in the memory cell array region, each of the main bit lines connecting the first and second non-volatile memory elements which are adjacent to each other in the row direction;
a plurality of column select gates each of which is provided in each of the main bit lines;
2
M
latch circuits, each of which is connected in common with each four of the column select gates;
2
N
input/output terminals(N<M); and
2
(M−N)
latch select gates provided between each of the 2
N
input/output terminals and the 2
(M−N)
latch circuits, the 2
(M−N)
latch circuits being connected in common to one of the 2
N
input/output terminals.
In this configuration, 2
M
bits (or 128 bytes, when M=10) of data of which the number of bits is greater than the number of I/O terminals may be simultaneously read or programmed between the 2
M
latch circuits and the memory cell array region.
When reading data, 2
M
bits of data (or 128 bytes, for example) is stored in the 2
M
(or 128×8, for example) latch circuits. After that, the 2
(M−N)
latch select gates provided between each of the 2
N
(or 8, when N=3) input/output terminals and the 2
(M−N)
(or 128, when M=10 and N=3) latch circuits may be sequentially turned on, so that 2
(M−N)
times operations can be performed to output the 2
M
bits of data from the 2
N
input/output terminals. Each of the latch circuits may include a sense amplifier.
Programming of data can be performed in the same manner as reading. Specifically, in data programming, the 2
(M−N)
latch select gates provided between each of the input/output terminals and the 2
(M−N)
latch circuits may be sequentially turned on, so that 2
(M−N)
times operations can be performed to write the 2
M
bits of data from the 2
N
input/output terminals to the 2
M
latch circuits.
In this file storage type non-volatile semiconductor memory device, each of the sector regions may include:
a plurality of block regions divided in the row direction;
a plurality of sub bit lines disposed in the column direction in each of the block regions, each of the sub bit lines being connected in common with the adjacent first and second non-volatile memory elements respectively belonged to two of the memory cells which are adjacent to each other in the row direction; and
bit line select gates each of which is disposed between each of the main bit lines and each of the sub bit lines in the same column as the main bit lines.
The load capacitance connected with the main bit line can be reduced by connecting only the sub bit lines in a selected block region to the main bit line through the bit-line select gates.
Each of the first and second non-volatile memory elements ma
Lebentritt Michael S.
Nguyen Tuan T.
Oliff & Berridg,e PLC
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