Non-volatile semiconductor memory device capable of...

Details Non-volatile semiconductor memory device capable of... Non-volatile semiconductor memory device capable of...

2002-10-30

2004-06-01

Lam, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S189090

Reexamination Certificate

active

06744672

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more specifically, to a non-volatile semiconductor memory device having a transistor passing current bidirectionally as a memory cell.
2. Description of the Background Art
Among non-volatile semiconductor memory devices, one type of flash EEPROM, namely an NROM (Nitride Read Only Memory) type flash EEPROM (hereinafter referred to as NROM) has been attracting attention. An NROM has an ONO (Oxide Nitride Oxide) film as a gate insulating film, and is capable of storing two bits of information per one memory cell. By employing the NROM, chip area per one bit may be reduced compared to other non-volatile semiconductor memory device having a floating gate. The NROM is disclosed in U.S. Pat. No. 6,081,456.
FIG. 10
is a circuit diagram related to an operation of applying potential to bit lines of a memory cell array of a conventional NROM.
Referring to
FIG. 10
, memory cell array
2
includes bit lines BL
1
to BL
5
, word lines WL
1
to WLn, memory cells
111
to
114
having their gates connected to the word line WL
1
, and memory cells
121
to
124
having their gates connected to the word line WLn.
In the memory cell array
2
, among a row of memory cells sharing the same word line, adjacent memory cells share one bit line. Specifically, memory cells
111
and
112
are connected to a bit line BL
2
at a node NB and thus share the bit line BL
2
. Memory cells
112
and
113
are connected to a bit line BL
3
at a node NA and thus share the bit line BL
3
.
When using a current sensing type sense amplifier circuit
12
(hereinafter referred to as “current sense amplifier circuit”), such as the one mounted on a conventional flash memory, with the memory cell array
2
thus structured, a switch circuit
504
switching potential applied to bit lines is structured as shown in FIG.
10
.
The switch circuit
504
includes switch units
531
to
535
provided corresponding to bit lines BL
1
to BL
5
, respectively.
The switch unit
531
includes an N-channel MOS transistor
542
connected between the read power source line
524
, which is supplied with read power source potential VddR via the sense amplifier circuit
12
, and the bit line BL
1
for receiving a control signal VG
1
at its gate. The switch unit
531
further includes an N-channel MOS transistor
544
connected between the ground power source line
522
, which is supplied with ground potential GND, and the bit line BL
1
for receiving a control signal GG
1
at its gate.
The switch unit
532
includes an N-channel MOS transistor
552
connected between the read power source line
524
and the bit line BL
2
for receiving a control signal VG
2
at its gate, and an N-channel MOS transistor
554
connected between the ground power source line
522
and the bit line BL
2
for receiving a control signal GG
2
at its gate.
The switch unit
533
includes an N-channel MOS transistor
562
connected between the read power source line
524
and the bit line BL
3
for receiving a control signal VG
3
at its gate, and an N-channel MOS transistor
564
connected between the ground power source line
522
and the bit line BL
3
for receiving a control signal GG
3
at its gate.
The switch unit
534
includes an N-channel MOS transistor
572
connected between the read power source line
524
and the bit line BL
4
for receiving a control signal VG
4
at its gate, and an N-channel MOS transistor
574
connected between the ground power source line
522
and the bit line BL
4
for receiving a control signal GG
4
at its gate.
The switch unit
535
includes an N-channel MOS transistor
582
connected between the read power source line
524
and the bit line BL
5
for receiving a control signal VG
5
at its gate, and an N-channel MOS transistor
584
connected between the ground power source line
522
and the bit line BL
5
for receiving a control signal GG
5
at its gate.
Next, data writing/reading to/from the memory cell will be described. In the memory cell array shown in
FIG. 10
, each of two bit lines opposite to each other with a memory cell therebetween can be connected to either one of the ground power source line
522
or the read power source line
524
. Such a structure allows to change the direction of voltage applied to the memory cell as desired. Each memory cell has two memory areas for enabling data writing/reading to/from different memory areas by changing the direction of the current. In the following, a description will be given focused on the memory cell
112
as a representative.
FIG. 11
is a diagram related to a data writing operation to a memory area L
1
of the memory cell
112
.
Referring to
FIG. 11
, potential of the bit line BL
2
is set to the write potential VddW and potential of the bit line BL
3
is set to the ground potential GND when writing data to the memory area L
1
. When the word line WL
1
is activated to H level, which is the write state, write current Iw
1
flows from the bit line BL
2
to the bit line BL
3
through the non-volatile memory cell
112
. At this time, data is written to the memory area L
1
.
FIG. 12
is a diagram related to a data reading operation from a memory area L
1
of the memory cell
112
.
Referring to
FIG. 12
, the bit line BL
3
receives the read power source potential VddR via current sense amplifier circuit
12
when reading data from the memory area L
1
. The bit line BL
2
is coupled to the ground potential GND. The threshold voltage of the memory cell with the potentials of the bit lines thus set is large, when the data is written to the memory area L
1
.
Once the potentials of the bit lines are set, the word line WL
1
is activated to H level of the read state. If the threshold voltage of the memory cell is lower than the H level of the read state, then the read current Ir
1
flows from the bit line BL
3
to the bit line BL
2
. By detecting the current value of this time with the sense amplifier circuit
12
, whether the data has been written to the memory area L
1
or not can be read out as information.
As described above, with respect to the memory area L
1
, directions of current at writing operation and reading operation are opposite.
FIG. 13
is a diagram related to a data writing operation to a memory area L
2
of the memory cell
112
.
Referring to
FIG. 13
, the bit line BL
3
is provided with the write power source potential VddW and the bit line BL
2
is coupled to the ground potential when writing data to the memory area L
2
. When the word line WL
1
is activated to H level of the write state, write current Iw
2
flows from the bit line BL
3
to the bit line BL
2
. At this time, data is written to the memory area L
2
.
FIG. 14
is a diagram related to a data reading operation from the memory area L
2
of the memory cell
112
.
Referring to
FIG. 14
, the bit line BL
2
is provided with the read power source potential VddR via the sense amplifier circuit
12
when reading data from the memory area L
2
. The bit line BL
3
is coupled to the ground potential GND.
The threshold voltage of the memory cell with the potentials of the bit lines thus set is large, when the data is written to the memory are L
2
. When the threshold voltage of the memory cell is small, by activating the word line WL
1
to the H level of the write state, the read current Ir
2
flows from the bit line BL
2
to the bit line BL
3
. By detecting the current value of this time with the sense amplifier circuit
12
, whether the data has been written to the memory area L
2
or not can be sensed.
As described above, with respect to the memory area L
2
also, direction of current at writing operation and reading operation are opposite.
In the conventional NROM, when data reading is to be performed, bit lines are set to the floating state, except for the bit lines connected to the selected cell at both sides.
For example, when data are read from the memory cell
112
, all transistors included in the switch units
531
,
534
and
535
are set to be non-conducti

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