Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-07-19
2004-08-24
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185190, C365S185280, C365S185290
Reexamination Certificate
active
06781880
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to non-volatile memory devices and in particular the present invention relates to erase circuitry of non-volatile memory devices.
BACKGROUND OF THE INVENTION
Memory devices can be designed and manufactured using numerous, different materials and storage techniques. For example, volatile dynamic memory devices are typically fabricated using storage capacitors. Data is stored by changing the capacitor charge, and data is retrieved by sensing the stored charge. Volatile static memory devices are designed using latch circuits to store data, and non-volatile memory devices, such as flash, use floating gate transistors to store data.
Erase operations in a Flash memory device typically start by writing a background of zero to all memory locations in an erase block that are to be erased. This operation is referred to as a Pre-program cycle. Then an erase pulse is applied to the block of memory. A memory state machine, or control circuitry, steps through the array and verifies that all locations are erased. If a location is not erased properly, the state machine applies another pulse and then verifies. The erase pulse application and verification steps are repeated until the block is erased.
A problem can be encountered in some flash memory devices due to excessive amounts of current that are drawn during the initial pulses of an erase operation. One technique used to erase memory cells is to apply a positive voltage to the source of the cells and a negative voltage to the control gate of the cells. The negative voltage on the gate further couples negatively an already programmed floating gate of the cell. A tunnel current is formed between the source to the floating gate due to the electric field, and a Gate Induced Drain Leakage current (GIDL). This current is a result of gate diode breakdown of the cell because the floating gate cell has a big negative voltage and the source has a large positive voltage. The electric field in the gate to source area causes a breakdown in the depletion region, which sends some of the current to the memory substrate.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for improved erase circuitry for non-volatile memory devices.
SUMMARY OF THE INVENTION
The above-mentioned problems with non-volatile memory and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a non-volatile memory device comprises an array of memory cells, a counter circuit coupled to count voltage pulses applied to the memory cells, a voltage pump circuit to generate an elevated voltage output from an input voltage, and control circuitry to adjust a current sourced by the voltage pump in response to an output of the counter circuit.
In another embodiment, a flash memory device comprises an array of floating gate memory cells, a first voltage pump coupled to produce an output voltage from an input voltage, a second voltage pump coupled in parallel to the first voltage pump to produce the output voltage from the input voltage, a counter to maintain a running count of voltage pulses applied to the array during erase and program operations, and control circuitry coupled to the first and second voltage pumps and the counter. The control circuit selectively activates the first and second voltage pumps in response to the running count of the counter.
A method of operating a pump circuit of a memory device comprises activating a first plurality of parallel voltage pumps while an output count of a counter circuit is equal to or less than X counts, such that the activated pumps provides an output voltage with a first current limit. The first plurality of pumps and a second plurality of pumps are activated while an output count of the counter circuit is greater than X counts, such that the first and second pumps provide the first output voltage with a second current limit that is greater than the first current limit.
A method of erasing a flash memory cell comprises applying a negative voltage to a control gate of the flash memory cell, and applying a series of positive voltage pulses to a source of the flash memory cell. A current limit of the positive voltage pulses increases based upon the number of positive voltage pulses applied.
REFERENCES:
patent: 4752699 (1988-06-01), Cranford, Jr. et al.
patent: 5463588 (1995-10-01), Chonan
patent: 5801987 (1998-09-01), Dinh
patent: 6385093 (2002-05-01), Bautista et al.
Leffert Jay & Polglaze P.A.
Micro)n Technology, Inc.
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