Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2002-05-23
2004-08-10
Nguyen, Minh (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S161000, C375S376000
Reexamination Certificate
active
06774689
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a clock generation circuit and, more particularly, to a multi-phase phase locked loop (PLL) architecture used for synchronizing an electronic subsystem. The clock generation circuit and PLL architecture can generate a first set of phase outputs interleaved with a second set of phase outputs, one or more of which can be forwarded to the electronic subsystem to synchronize its operation. The circuit preferably includes a triple input phase detector that receives a first pair of phase outputs from a first set of phase outputs and a second phase output from a second set of phase outputs and, depending on the difference between an edge of the second phase output and an edge of the first pair of phase outputs, the phase detector delays the phase outputs of the second set of phase outputs relative to the first set of phase outputs.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Modern high-speed data communication systems typically use internal clock-referenced circuitry. The circuitry is designed to synchronize with, for example, an incoming data stream or reference signal. In most instances, a PLL circuit derives a sampling frequency from locking to the incoming data stream and generating the necessary clocking signals to which the receive circuitry is synchronized. Clock recovery circuits can employ a multi-phase PLL architecture, where the multiple phases' aid in sampling, and in some cases over-sampling a transmitted data stream. By establishing phase coherence between the PLL based clocks and the data, information can be extracted through this synchronous detection method.
In its most basic form, a PLL consists of a phase/frequency detector, a filter, control circuitry, and a variable oscillator. The signal generated by the oscillator is continuously compared against an incoming reference clock signal. The reference clock signal preferably transitions from edges of, for example, the incoming data stream. Once compared, the control circuitry adjusts the oscillator output frequency so that the incoming data stream and the oscillator output are transitioning at the same frequency and ideally in phase with one another. Thus, PLLs can be used for the synchronization and re-timing of transmission input data in the form of clock signals.
Clock recovery circuits employing PLLs often benefit by producing a multi-phase oscillator output. For example, a single-phase oscillator output may transition at the same frequency and phase as the incoming data stream. If, however, the clock recovery is designed to receive higher data-rate frequencies, it can be advantageous to design the receiver architecture using a parallel circuit design approach that permits the majority of the receiver to operate at lower frequencies. The oscillator in the receiver can generate multiple phases which are separated by a fixed phase angle such that if two phases are separated by a fixed phase angle, the data receiver circuits can be clocked at a higher frequency to at least match that of the incoming data stream. Thus, PLLs used for data transceivers in clock recovery applications can benefit from using multi-phase clocks to effectively increase the sampling or synchronization rate of higher input frequency events with lower speed clock signals.
If the oscillator of the PLL can generate multiple phases, a parallel receiver architecture can be designed whereby a higher frequency incoming data stream can be clocked and sampled by a substantially lower frequency sampling clock using multiple phases whereby the effective sampling rate can be very high. This scheme can thereby permit the phase detector to more accurately track the higher bit rate of the incoming data. SONET bit streams may have a bit rate as high as 10 bit/s or even 40 Gbit/s (e.g., SONET/SDH standard OC-192 specifies a transmission rate of 9953.28 Mbit/s, and OC-768 specifies a transmission rate of 39813.12 Mbit/s). Consequently, the PLL and other components of the clock recovery circuit design strike a trade off between a parallel multi-phase architecture operating at lower speed compared to a full-rate, higher-speed design, if in fact the higher-speed single phase output design is even possible.
Unfortunately, it is not always a simple matter to produce multiple phase outputs from an oscillator, especially when the incoming data stream has bit rates in the Gbit/s range. As the number of phase outputs increase, the outputs from each inverter within a long chain of inverters used by an oscillator will have extremely small delay tolerance. For example, if a 45° out-of-phase condition is desired (i.e., an 8-phase oscillator output is needed), then even the slightest process variation used in forming the oscillator will negatively effect the oscillator's ability to produce regularly spaced, 8-phase outputs separated ideally at 45°. The problem is compounded as the number of phase outputs or oscillator frequency increases, thereby causing a conflict between the oscillator speed (or tap-to-tap delay) and the number of phase outputs. Conventional tap-to-tap delay bandwidth necessary to propagate a high-speed signal becomes semiconductor fabrication process limited. Moreover, tap-to-tap delay interpolation using analog techniques proves unreliable at high oscillation frequencies over full semiconductor fabrication process corners.
It would be desirable to introduce a clock generation architecture that can use multi-phase outputs from an oscillator without the aforesaid drawbacks. The desired clock generation circuit can receive a high-speed incoming data stream in excess of several Gbit/s to, for example, 10 Gbit/s. Moreover, the desired clock generation architecture should be designed to utilize an oscillator in a PLL that produces, for example, one-half of the multi-phase outputs, while another portion of the PLL circuit produces the other half of the multi-phase outputs. In this fashion, the tap-to-tap delay within the oscillator can be kept fairly large thereby not unduly taxing the semiconductor fabrication process corners when the oscillator is called upon to operate in the GHz range. In addition to its high speed, high density phase output capability, the desired PLL circuit should beneficially interleave sets of delay outputs, each operating at the same frequency and time delay amount across all process variations. Accordingly, the clock generation circuit, the PLL (and associated oscillator), and the control circuits of the desired electronic subsystem should be formed on the same monolithic substrate using conventional semiconductor fabrication processing techniques—even when called upon to produce a large number of phase outputs and operate at significantly high frequencies.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by an improved clock generation circuit and, more particularly, to a PLL architecture that can find application in a clock and data recovery circuit. The PLL circuit includes an oscillator having a first set of delay circuits that can be coupled in a ring topology. The PLL circuit can also include a second set of delay circuits separate and apart from the oscillator. The phase outputs from the second set of delay circuits are delayed with respect to phase outputs from the first set of delay circuits in order for phase outputs from the first and second sets of delay circuits to be interleaved with one another. Accordingly, the combined number of first and second sets of delay circuits produce the requisite number of phase outputs from the clock generation circuit. However, only approximately one-half of the total number of phase outputs can occur from the first set of delay circuits—i.e., the oscillator. If the oscillator is called upon to operate at substantially higher frequencies, then the tap-to-tap delay can be kept fairly large, yet a high density, multi-phase output can be achieved from the combi
Conley & Rose, P.C.
Cypress Semiconductor Corp.
Daffer Kevin L.
Nguyen Minh
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