Field effect transistor square multiplier

Details Field effect transistor square multiplier Field effect transistor square multiplier

2001-04-09

2004-11-09

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific input to output function

Combining of plural signals

C327S349000, C327S359000

Reexamination Certificate

active

06815997

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of analog signal processing, and in particular to squaring an input signal by using field effect transistors operated in the saturation region to obtain an output signal that is proportional to the square of the input signal.
2. Description of the Related Art
In the field of analog signal processing very often a square output of an input signal is required. Since field effect transistors provide a plurality of advantages over bipolar transistors, for example, with respect to power consumption, a great deal of effort has been made in developing analog circuits that include squaring circuitry using field effect transistors instead of bipolar transistors. In most of these analog circuits, such as in four-quadrant multipliers, for a squaring stage of the circuit, the square relationship of the drain current I
DS
with respect to the difference of the gate-source voltage V
GS
and the threshold voltage of a field effect transistor V
Th
is employed when operated in the saturation region. The saturation region of a field effect transistor is defined as the region in which the voltage applied to the drain-source terminals V
DS
is higher than the difference of V
GS
and V
Th
. In this operation mode, the drain current is given by the following equation:
I
DS
=K
(
V
GS
−V
Th
)
2
,
where K=½ &mgr;
0
C
OX
(W/L) is the transconductance parameter, wherein &mgr;
0
is the effective surface mobility, C
OX
is the gate capacitance per unit area and W/L is the aspect ratio of the transistor channel width W and the transistor channel length L. Despite this inherent square relationship between the drain-source current and the gate-source voltage, it is nevertheless difficult to realize a simple and efficient circuit providing a pure square output signal, wherein variation of transistor characteristics does not adversely affect operation of the circuit.
The document “An MOS Four-Quadrant Analog Multiplier Using Simple Two-Input Squaring Circuits with Source Followers” by Ho-Jun Song and Choong-Ki Kim, published in IEEE Journal of Solid-State Circuits, Vol. 25, No. 3, June 1990, describes a four-quadrant multiplier based on the square-algebraic identity (V
1
+V
2
)
2
−(V
1
−V
2
)
2
=4V
1
V
2
and using the above-mentioned square law of MOS transistors. The multiplier includes circuits for squaring the sum and the difference of two differential input signals. Each squaring circuit comprises two MOS transistors acting as source followers, two so-called squaring transistors and a load, such as a resistor. However, the squaring circuits in this document require that the aspect ratio of the source followers be much larger than the aspect ratio of the squaring transistors, and that the drain current of the squaring transistors be less than a bias current flowing through the squaring transistors and the source followers, so that the gate-to-source voltage drop of the source followers can be regarded as constant. The constant gate-to-source voltage drop is necessary to obtain the required squaring of the sum and the difference, respectively, of the input signals. Moreover, it is difficult to provide MOS transistors that fulfill the condition regarding their aspect ratio mentioned above.
The document “A Four-Quadrant CMOS Analog Multiplier for Analog Neural Networks,” by N. Saxena and J. J. Clark, published in IEEE Journal of Solid-State Circuits, Vol. 29, No. 6, June 1994 describes a four-quadrant analog multiplier with 5 n-MOS field effect transistors and two current mirrors. The operation of the four-quadrant multiplier is based on the algebraic identity (V
1
+V
2
)
2
−V
1
2
−V
2
2
=2V
1
V
2
and provides an output current I
out
=−2K V
in1
V
in2
. The multiplier, however, does not provide a squared signal of the input signals, but instead creates respective drain currents in the transistors that are proportional to the square of the differences of the input voltages and the threshold voltages of the transistors. Since the MOS transistors are identical, summation of the individual drain currents eliminates the threshold voltages and produces an output voltage that is given by I
out
=−2K V
in1
V
in2
.
The document “A CMOS Four-Quadrant Analog Multiplier with Single-Ended Voltage Output and Improved Temperature Performance,” by Z. Wang, published in IEEE Journal of Solid-State Circuits, Vol. 26, No. 9, September 1991 discloses a multiplier consisting of a differential transconductor based on the square-difference technique, a scaled floating-voltage pair generator, an MOS resistor, and a bias generator. The MOS transconductor uses 2 cross-coupled pairs of MOS transistors operated in the saturation region. A floating bias voltage is applied between the gates of a respective pair of transistors. The circuit provides an output current that is proportional to the input voltage times the bias voltage, rather than an output current that is proportional to the square of the input signal.
Since producing the square of an input signal is required for a plurality of electronic devices and methods, such as measuring the root mean square value of any type of signal, there exists a need for an improved square multiplier providing fast signal performance while exhibiting low power consumption.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a field effect transistor (FET) square multiplier for squaring an input signal is provided, comprising a first field effect transistor formed on a substrate and having a gate, a source, a drain and a channel, the gate of the first field effect transistor connected to receive a sum of the input signal and a reference signal. The FET square multiplier also comprises a second field effect transistor formed on the substrate and having a gate, a source, a drain and a channel, the gate of the second field effect transistor connected to receive a difference of the input signal and the reference signal, wherein the first and second field effect transistors have a first aspect ratio of channel width to channel length, a first gate insulation layer capacitance per unit area and a first charge carrier mobility. The FET square multiplier also comprises a third field effect transistor formed on the substrate and having a gate, a source, a drain and a channel, the gate of the third field effect transistor connected to receive the reference signal, the third field effect transistor having a second aspect ratio of channel width to channel length, a second gate insulation layer capacitance per unit area and a second charge carrier mobility. Additionally, the FET square multiplier comprises a constant current source connected to the source of the first, second and third field effect transistors, respectively; wherein the drain of the first field effect transistor is connected to the drain of the second field effect transistor, and a parameter value defined as the product of aspect ratio, gate insulation layer capacitance per unit area and charge carrier mobility of the third field effect transistor is two times the corresponding parameter value of the first and second field effect transistors, wherein the field effect transistor square multiplier is adapted to provide a current I
1
at a common node connected to the drain of the first and second field effect transistors and a current I
2
at the drain of the third field effect transistor, wherein a difference of I
1
and I
2
is proportional to the square of the input signal when the first, second and third field effect transistors are operated in the saturation region.
According to another aspect of the present invention, an analog signal processing unit is provided, the analog signal processing unit comprising a plurality of square multipliers cooperatively connected to form an output signal in response to at least one input signal, the output signal representing a predefined function of the at least one input signal. In t

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