Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2000-10-27
2004-12-21
Mai, Tan V. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S253000, C708S254000
Reexamination Certificate
active
06834291
ABSTRACT:
BACKGROUND OF THE PRESENT INVENTION
The present application concerns pseudo-random generators, in particular gold code generators.
Pseudo-random generators have applicability for a number of communication systems, in particular, for spread spectrum wireless communications. In spread spectrum transmissions, the circuit artificially spreads the transmitted signals bandwidth by modulating an information signal, either in phase or frequency, with a pseudo-random sequence that occurs at a greater rate than that required for the data alone. During signal reception, the receiver synchronizes an internal pseudo-random generator to the pseudo-random sequence of the transmitted signal to fully recover the available power and decode the message. Most direct sequence spread spectrum systems pseudo-randomly modulate the phase of the RF carrier signal 10 times or greater than the rate required for the data transmission. This results in a signal spectrum which is much broader than would be occupied if the RF carrier signal were modulated by only the data stream. Frequency hopping systems use the pseudo-random generator to implement frequency hops within the spread spectrum range.
Matching pseudo-random generators at the transmitter and receiver allow the correlation and recovery of the information signal. Other transmitted signals with different pseudo-random codes can be transmitted in the same bandwidth since the correlation between the different pseudo-random codes is quite low. The transmissions using the different pseudo-random codes will tend not to significantly interfere with one another.
One way of implementing a pseudo-random generator is with a linear feedback shift register (LFSR). Taps from the linear feedback register are sent to a logic circuit to create a new input (feedback) bit. The linear shift register runs through a large number of different codes before repeating. The linear feedback shift register is preferably selected with a feedback path producing the maximum code length. Also beneficial for the linear shift register is low auto-correlation with shifts in the pseudo-random sequence and low cross-correlation with other sequences.
One preferred way of implementing a pseudorandom sequence is to combine the outputs of two linear feedback shift registers. Such a pseudo-random generator is called a gold code generator.
FIG. 1
illustrates a gold code generator used with the UMTS European wireless standard. The gold code generator is constructed of two linear feedback shift registers. The first linear feedback shift register has feedback taps from registors
0
and
3
. The second linear feedback shift register has feedback taps at registors
0
,
1
,
2
, and
3
. The first serial linear feedback shift register's output is combined with the output of the second linear feedback shift register in the EXCLUSIVE-OR
40
. The first linear feedback shift register
42
has taps at registers
4
,
7
and
18
that go to a EXCLUSIVE-OR (mask)
44
. The second linear feedback shift register
46
has taps at registers
4
,
6
, and
17
fed to the EXCLUSIVE-OR
48
. The output to the EXCLUSIVE-ORs
44
and
48
are sent to a second output EXCLUSIVE-OR
52
.
It is desired to have an improved implementation of a gold code generator.
SUMMARY OF THE PRESENT INVENTION
The inventors have noticed that the range of taps used to implement the second output of the UMTS gold code generator standard is quite broad: In the first linear shift register between taps
4
and
18
and in the second linear shift register between taps
4
and
17
. This broad range of taps makes it difficult to implement a parallel implementation of the gold code generator in arithmetic logic units or other computational units that operate on parallel data.
Since the second output is in fact a delayed version of the first output, the gold code generator can be implemented by forming two pairs of linear feedback shift registers and using different seeds for the second pair of linear feedback shift registers. This significantly reduces the range of the output taps in any of the linear feedback shift registers, and makes it easier to implement a parallel implementation of the gold code generator to produce multiple output bits.
One embodiment of the present invention comprises a gold code generator comprising two pairs of linear feedback shift registers wherein the second seed values for the second pair of linear feedback shift registers are different from the first seed values for the first pair of linear feed back state machines. The second seed values are calculated from the first seed values, wherein the first and second pair of linear feedback shift registers are implemented to produce more than one input bit and more than one output bit for each linear feedback shift registers at the same time.
Another embodiment of the present invention comprises at least one reconfigurable chip implementing a gold code generator, the at least one reconfigurable chip including background and foreground configuration memories. The background configuration memory is adapted such that it can be loaded with a gold code generator configuration while the at least one reconfigurable chip configured with the foreground configuration operates. After the background configuration is loaded with the gold code generator configuration, the background plane is activated to reconfigure the at least one reconfigurable chip.
Another embodiment of the present invention comprises a method of implementing a pseudo-random code generator comprising the steps of converting a pseudo-random code generator specification into an equivalent representation. The pseudo-random code generator specification being such that taps used to calculate an output include at least one tap within n spaces of the input. Equivalent representation is such that no taps are within n spaces from the input. The method includes implementing the equivalent representation such that n new state bits are calculated at the same time.
Another embodiment of the present invention is a method of implementing a pseudo-random code generator, the method comprising converting a pseudo-random code generation specification into an equivalent of representation. The pseudo-random code generator specification being such that taps used to calculate an output bit are defined within a first shift register span, the equivalent representation is such that taps used to calculate an output bit within a smaller shift register span. The method includes implementing the equivalent representation such that multiple new bit states are calculated at the same time.
REFERENCES:
patent: 5111416 (1992-05-01), Harada
patent: 5566099 (1996-10-01), Shimada
patent: 5966534 (1999-10-01), Cooke et al.
patent: 5970254 (1999-10-01), Cooke et al.
patent: 6192385 (2001-02-01), Shimada
patent: 2001/0033663 (2001-10-01), Ishimoto et al.
Theory and Application of Pseudonoise Sequences, CDMA Systems Engineering Handbook, Jhong Sam Lee and Leonard E. Miller (1998), pp. 543-675.
Pugh Daniel J.
Rollins Mark
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Mai Tan V.
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