Image analysis – Image enhancement or restoration – Artifact removal or suppression
Reexamination Certificate
2001-08-27
2004-12-07
Boudreau, Leo (Department: 2624)
Image analysis
Image enhancement or restoration
Artifact removal or suppression
C345S087000, C345S204000, C348S614000, C348S790000, C352S160000
Reexamination Certificate
active
06829392
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to an image processing circuit as well as an image data processing method suited for application to an electrooptic device, wherein video signals obtained by dividing a video signal into a plurality of channels and extending the time axis thereof, so as to maintain a predetermined signal level every unit time, are fed to corresponding data lines at a predetermined timing. Also, it relates to an electrooptic device and electronic equipment which employ such a processing circuit or method.
2. Description of Related Art
A conventional electrooptic device, for example, an active matrix-type liquid-crystal display device, will be explained with reference to
FIGS. 11 and 12
. First, as shown in
FIG. 11
, the conventional liquid-crystal display device is constructed of a liquid-crystal display panel
100
, a timing circuit
200
, and a video signal processing circuit
300
. The timing circuit
200
outputs timing signals for use in various portions. The video signal processing circuit
300
can include a D/A converter circuit
301
that converts image data Da supplied by external equipment from a digital signal into an analog signal and outputs the resulting signal as a video signal VID. Further, a phase expansion circuit
302
can be included that expands the received video signal VID of one channel into video signals of N phases (N=6 in the figure) and outputs the resulting video signals. Here, the video signal is expanded into N phases by a sampling circuit so that a time period for which the video signal fed to thin film transistors (TFTs) is applied is lengthened, thereby sufficiently securing a sampling time period for the data signals and a charge/discharge time period for the TFT panel
100
for the data signals.
In turn, an amplifier/inverter circuit
303
subjects the video signals to polarity inversion under the following conditions and amplifies the inverted signals as required, so as to feed phase-expanded video signals VID
1
-VID
6
to the liquid-crystal display panel
100
. Here, “polarity inversion” signifies alternately inverting the voltage levels of the video signals with respect to a reference potential set at the center potential of the amplitudes of the video signals. Besides, the inversion of the video signals is done when the method of applying the data signal is (1) polarity inversion in scanning line units, (2) polarity inversion in data signal line units, or (3) polarity inversion in pixel units, and the inversion period is set at one horizontal scanning period or one dot clock period.
The liquid-crystal display panel
100
can be constructed so that an element substrate and a counter substrate are opposed to each other with a gap defined therebetween, and a liquid crystal is enclosed in the gap. Here, each of the element substrate and the counter substrate can be made of a quartz substrate, a hard glass, or the like.
In the element substrate, a plurality of scanning lines
112
are arrayed and formed in parallel so as to extend in the X-direction in
FIG. 12
, while a plurality of data lines
114
are formed in parallel so as to extend in the Y-direction orthogonal to the scanning lines
112
. Here, the data lines
114
are divided into blocks each consisting of six lines, and the blocks are termed “blocks B
1
-Bm”. For brevity of the ensuing explanation, when referring to the data lines in general, they will be designated by the reference numeral
114
, but when referring to specified ones of the data lines
114
, they will be designated by reference numerals
114
a
-
114
f.
At the intersection points between the scanning lines
112
and the data lines
114
, TFTs
116
are connected as switching elements, by way of example. More specifically, the gate electrodes of the TFTs
116
are connected to the scanning lines
112
, while the source electrodes thereof are connected to the data lines
114
, and the drain electrodes thereof are connected to pixel electrodes
118
. Individual pixels are configured of the pixel electrodes
118
, a common electrode formed on the counter substrate, and the liquid crystal sandwiched in between both the electrodes, and they are arrayed in the shape of a matrix at the intersection points between the scanning lines
112
and the data lines
114
. Incidentally, retention capacitors (not shown) are further formed in a state where they are respectively connected to the pixel electrodes
118
.
Meanwhile, a scanning line driver circuit
120
can be formed on the element substrate, and the scanning line driver circuit
120
outputs pulse-like scanning signals to the respective scanning lines
112
in succession on the basis of a clock signal CLY, the inverted clock signal CLYinv thereof, a transfer start pulse DY, etc. delivered from the timing circuit
200
. More specifically, the scanning line driver circuit
120
successively shifts the transfer start pulse DY fed at the beginning of a vertical scanning period in accordance with the clock signal CLY and the inverted clock signal CLYinv, and it outputs the resulting signals as scanning line signals, to thereby successively select the respective scanning lines
112
.
On the other hand, a sampling circuit
130
includes a sampling switch
131
at one end of each of the data lines
114
. The switches
131
can be made of TFTs which are also formed on the element substrate, and the source electrodes of these switches
131
are fed with the corresponding video signals VID
1
-VID
6
through video signal feed lines L
1
-L
6
. Besides, the gate electrodes of the six switches
131
connected to the data lines
114
a
-
114
f
of the block B
1
are connected to a signal line which is fed with a sampling signal S
1
, and those of the six switches
131
connected to the data lines
114
a
-
114
f
of the block B
2
are connected to a signal line which is fed with a sampling signal S
2
. Likewise, the gate electrodes of the six switches
131
connected to the data lines
114
a
-
114
f
of the block Bm are connected to a signal line which is fed with a sampling signal Sm. Here, each of the sampling signals S
1
-Sm is a signal for sampling the video signals VID
1
-VID
6
every block within a horizontal effective display period.
A shift register circuit
140
is also formed on the element substrate, and the shift register
140
outputs the sampling signals S
1
-Sm in succession on the basis of a clock signal CLX, the inverted clock signal CLXinv thereof, a transfer start pulse DX, etc. delivered from the timing circuit
200
. More specifically, the shift register circuit
140
successively shifts the transfer start pulse DX fed at the beginning of the horizontal scanning period in accordance with the clock signal CLX and the inverted clock signal CLXinv, and it successively outputs the resulting signals as the sampling signals S
1
-Sm.
In such a construction, when the sampling signal S
1
is outputted, the video signals VID
1
-VID
6
are respectively sampled by the six data lines
114
a
-
114
f
belonging to the block B
1
, and they are respectively written into the six pixels associated with the selected scanning lines at the current time by the corresponding TFTs
116
.
Thereafter, when the sampling signal S
2
is outputted, the video signals VID
1
-VID
6
are respectively sampled by the six data lines
114
a
-
114
f
belonging to the block B
2
, on this occasion, and they are respectively written into the six pixels associated with the selected scanning lines at that time by the corresponding TFTs
116
.
Likewise, when the sampling signals S
3
, S
4
, . . . and Sm are successively outputted, the video signals VID
1
-VID
6
are respectively sampled by the six data lines
114
a
-
114
f
belonging to the blocks B
3
, B
4
, . . . and Bm, and they are respectively written into the six pixels associated with the selected scanning lines at those times. Then, the next scanning lines are subsequently selected, and similar write operations are repeatedly executed in the blocks B
1
-Bm.
With the above driving syste
Boudreau Leo
Edwards Patrick L.
Oliff & Berridg,e PLC
Seiko Epson Corporation
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