Thermal gradient enhanced CVD deposition at low pressure

Coating processes – Coating by vapor – gas – or smoke

Reexamination Certificate

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C427S255500, C427S255390, C427S585000

Reexamination Certificate

active

06780464

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to methods and apparatus for chemical vapor deposition onto a substrate, and more particularly to a method that deposits silicon at a high rate due to enhanced mass transport by thermal diffusion, i.e., the “Soret effect”, by using a temperature gradient above the substrate surface.
2. Description of the Prior Art
The semiconductor industry has been depositing poly crystalline silicon for a number of years. The method of choice for most applications is a Low Pressure Chemical Vapor Deposition (LPCVD) process. The LPCVD process is a well studied art wherein poly crystalline silicon deposition is accomplished by placing a substrate in a vacuum chamber, heating the substrate and introducing silane or any similar precursor such as disilane, dichlorosilane, silicon tetrachloride and the like, with or without other gases. The reactant gases are usually pre-heated prior to passing over a wafer when a rapid deposition is required. The pre-heating pre-activates the reactants and increases the rate of subsequent deposition. A disadvantage of this process is that it causes gas reactions that deplete the supply of available reactants which partially defeats the effect of pre-activation in increasing the deposition rate. Deposition rates of approximately 10 to 100 angstroms per minute are typical for low-pressure processes (less than 1 Torr) in a hot wall low pressure reactor. Deposition rates of 20 to 300 angstroms per minute are achieved in a vertical flow reactor with deposition rates as high as 500 angstroms per minute. Silicon deposition rates over 10,000 angstroms per minute have been reported, however these high deposition rates do not produce poly crystalline silicon films that are useful in manufacturing semiconductor devices because the resulting poly crystalline silicon has undesirable features such as large grain size, non uniform thickness, etc. Deposition rates of approximately 3000 angstroms per minute of useful semiconductor quality poly crystalline silicon are achieved with a higher pressure process (25 to 350 Torr) as described in detail in U.S. Pat. No. 5,607,724.
A typical prior art CVD system is illustrated in
FIG. 1
, and includes a reaction chamber
12
having a quartz tube
14
. The chamber is enclosed on a first end by a seal plate
16
that can be removed for installation and removal of a boat
18
carrying substrates
20
. A reactant gas
22
such as silane or similar precursor and hydrogen and a dopant gas such as phosphine are supplied to the chamber
12
through ports
24
and
25
to tubing
27
and flow through the chamber
12
and exit the exhaust port
26
. A plurality of heater elements
28
are separately controlled and adjustable to compensate for the well known depletion of feed gas concentration as the gas
22
flows from the gas injection tube
27
to the exhaust port
26
. The system of
FIG. 1
typically operates at a gas chamber pressure in the range from 100 to 200 mTorr, and at a gas flow rate from 100-200 sccm. The reactant gas is usually silane diluted with hydrogen. Operating in the low pressure range of 100-200 mTorr with silane, or other similar precursor, results in a low deposition rate, typically in the range of 10 to 100 angstroms per minute, and 5 to 30 angstroms per minute if a dopant gas is introduced. The resulting surface roughness is typically 10-15 nm. Operation at higher concentrations of the reactant gases results in non-uniform deposition across the substrates, as well as large differences in the deposition rate from substrate to substrate. Increasing the gas flow rate in the chamber of
FIG. 1
can improve deposition uniformity at higher pressures, but has the disadvantage of increasing the gas pressure resulting in gas phase nucleation causing particles to be deposited on the substrate.
There are other problems associated with the reactor of
FIG. 1
, such as film deposition on the interior surfaces of the quartz tube
14
causing a decrease in the partial pressure of the reactive feed gas concentration near the substrate surface. This results in a reduced deposition rate and potential contamination due to film deposited on the wall of tube
14
flaking off and falling on the substrate
20
surfaces. Another problem occurs due to the introduction of a temperature gradient applied between the injector end and exhaust end of the tube to compensate for the depletion of reactive chemical species from the entrance to the exit. As a result of this temperature gradient, the deposited poly crystalline silicon grain size varies from substrate to substrate, i.e. across the load zone, because the grain size is temperature dependent. This variation in grain size from substrate to substrate can result in variations of poly crystalline silicon resistivity and difficulties with the subsequent patterning of the poly crystalline silicon resulting in variations in the electrical performance of the integrated circuits produced.
A prior art vertical flow reactor
30
is illustrated in FIG.
2
. This reactor is capable of deposition rates as high as 500 angstroms per minute. The substrates
32
are placed in a substrate carrier
34
in the reactor
30
. The reactor chamber
36
is confined by a quartz bell jar
38
and a seal plate
40
. The bell jar
38
is surrounded by a heater
42
for heating the substrates
32
to the required temperature. The reactant gases such as silane and hydrogen are introduced through ports
44
and
46
, and flow through the gas injection tube
48
to the injector
50
, across the substrate
32
and out the exhaust port
52
. The arrangement of
FIG. 2
greatly reduces the gas depletion effect experienced with the device of
FIG. 1
, and thereby allows an increased gas flow which results in an increased deposition rate of up to 500 angstroms per minute. Two major problems are associated with the apparatus of FIG.
2
. In operation, the injection tube
48
and injector
50
are at the same temperature as the substrates
32
, a condition that results in silicon deposition in and on the injection tube
48
and injector
50
, which then flakes off and is deposited as particles on the substrate
32
. The other major problem is that the substrates
32
are not at the same temperature due to the method of heating the substrates from heater
42
with no heater below the substrates. The non-uniform heating causes a non-uniform silicon deposition over the substrates
32
as poly crystalline silicon deposition is a surface reaction rate limited process, which is very temperature dependent.
FIG. 3
shows a prior art single substrate reactor
54
that overcomes some of the problems associated with the reactors of
FIGS. 1 and 2
. This is described in detail in U.S. Pat. No. 5,607,724. A substrate
56
is placed on a rotating pedestal
58
in chamber
54
. Upper lamps
62
and lower lamps
63
radiate energy through transparent chamber walls
64
and
66
to uniformly heat the substrate
56
. The pedestal
58
is turned to rotate the substrate
56
, which is heated on both sides by the lamps. The substrate temperature is therefore uniform over its surface, which results in a uniform poly crystalline silicon deposition on the substrate
56
. The reactor
54
does not have an injector in the chamber, which eliminates the problem of deposition on the injector
50
shown in FIG.
2
. The reactant gas
67
is supplied through an inlet port
68
and exits exhaust port
70
. The major problem associated with the reactor of
FIG. 3
is the limited throughput, i.e. the number of substrates processed per hour. This problem can be addressed by increasing the operating pressure to 10 Torr or greater resulting in high deposition rates exceeding 1000 angstroms per minute, however operating the reactor at such high pressures can result in a gas phase reaction where silicon particles are formed in the gas and deposited on the substrate. Another problem associated with the reactor is the tendency for silicon deposition on the quartz walls
64
,
66
resulting i

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