Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Treating electrolytic or nonelectrolytic coating after it is...
Reexamination Certificate
2002-03-26
2004-12-07
Koehler, Robert R. (Department: 1775)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Treating electrolytic or nonelectrolytic coating after it is...
C205S157000, C205S225000, C427S533000, C438S758000
Reexamination Certificate
active
06827835
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for electroplated metal annealing process, and more particularly, to a method for electroplated copper annealing process.
2. Description of the Prior Art
As is well known to those skilled in the art, the RC delay of interconnects would limit the device high-speed performance while the dimensions of ULSI devices continue to shrink. The implementation of Cu (resistivity 1.7 m&OHgr;-cm) can effectively address this issue. Moreover, low fabrication cost and good reliability are some of the key reasons for replacing Al metallization by Cu. Electroplating is the preferred deposition method for Cu metallization due to its low capital cost, high throughput, excellent filling capability, good electrical characteristics and compatibility with low K materials. The room-temperature self-annealing behavior of electroplated (ECP) copper and its impact on device manufacturing have led to investigation of a post ECP annealing process to stabilize copper film properties before chemical mechanical polishing (CMP). The re-crystallization behavior would lead to a maximum sheet resistance drop of approximately 18~20% for 1 micron ECP Cu film before stabilizing. In addition, the self-annealing phenomenon causes an increased CMP polishing rate of ECP Cu films as a result to drop in film hardness. Therefore, a thermal anneal process is an essential step to stabilize the electroplated Cu films before CMP.
Post ECP Cu annealing process is generally done in a batch process using a furnace where typical annealing time is 30 minutes at elevated temperatures such as 350° C. in a vacuum or N
2
atmosphere.
FIG. 1
is a schematic view showing the structure of the electroplated copper, a large number of hillock defects
102
were found in the electroplated copper lattice
101
after high temperature post-ECP annealing. Currently, low temperature annealing process (<200° C.) is a trend to suppress such hillock defects. However, after CMP, enormous hillock defects still appear after Cu barrier layer deposition and become large as follow-up dielectric film deposition in the damascene process.
Therefore, in order to overcome the above-mentioned defects, there is a need to develop new methods to solve the problems.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for electroplated metal annealing process that substantially overcomes the above-mentioned defects which arise from conventional methods.
Accordingly, it is an object of the present invention to provide a novel method for an electroplated metal annealing process by replacing the conventional furnace post-ECP Cu annealing process with a NH
3
plasma process.
It is another object of this invention to provide a method for suppressing the formation of hillock type defects in the electroplated copper by using the high temperature NH
3
plasma to effectively release the stress in the electroplated copper.
It is an object of the present invention to provide a method for reducing the post-CMP defects such as pullouts and line voids.
In accordance with the above-mentioned objects, the present invention relates to providing a method for electroplated metal annealing process. First, a semiconductor structure is provided, wherein the semiconductor structure has a plurality of semiconductor components, such as a gate electrode, a source region and a drain region, and a field oxide region. Second, a dielectric layer is formed over the semiconductor structure, and a via which exposes a part of the semiconductor structure is formed in the dielectric layer by the use of the conventional lithographic and etching process, and an electroplated metal layer is formed over the dielectric layer; meanwhile, the via is filled with the electroplated metal layer. The electroplated metal layer then is annealed by a NH
3
plasma-enhanced chemical vapor deposition process. By the use of implementing a NH
3
plasma annealing process to replace a conventional furnace ECP post annealing process, it can effectively suppress the formation of hillock type defects due to the reduction in the stress in the copper layer, which could reduce the occurrence of defects such as pullouts and line voids in the following-up step. Meanwhile, the method could eliminate the re-formation of hillock type defects in the following barrier layer depositions, and it is a faster and more economical process for electroplated copper annealing due to the fact that the key operation time of the process is only about 30 seconds to 300 seconds, which is much less than the time of the conventional furnace ECP post-annealing process (30 minutes).
REFERENCES:
patent: 2003/0162392 (2003-08-01), Wang et al.
Hsieh Tsung-Tang
Huang Kuo Feng
Yang Neng-Hui
Dickinson Wright PLLC
Koehler Robert R.
United Microelectronics Corp.
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