Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2001-02-28
2004-08-03
Thomas, T. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S443000, C257S750000, C257S766000
Reexamination Certificate
active
06770978
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to metal lines used for flat panel display devices such as a liquid crystal display (LCD), a field emission display (FED), an electrophoretic display (EPD), a plasma display (PDP), an electrochromic display (ECD) and an electroluminescent display (ELD), a flat panel type image sensor employing an active matrix substrate, a printed wiring board employing a ceramic substrate and metal lines used in a variety of other fields, a method for fabricating the metal lines, a thin film transistor employing the metal lines and a display device.
In a flat panel display represented by the liquid crystal display (LCD), there is adopted a drive system holding a display material such as liquid crystals between a pair of substrates and applying a voltage to this display material. In this case, electric interconnecting lines made of a conductive material are arranged at least on one substrate.
For example, in the case of an active matrix drive type LCD, gate electrodes and data electrodes are arranged in a matrix form on one substrate (active matrix substrate) of a pair of substrates that hold the display material between them, and thin film transistors (TFTs) and pixel electrodes are arranged at the intersections of them. Normally, these gate electrodes and data electrodes are formed of a metal material of tantalum (Ta), aluminum (Al), molybdenum (Mo) or the like and formed into a film by a dry system film forming method such as the sputtering method.
If it is attempted to increase the area and improve the resolution of such a flat panel display, then a drive signal delay emerges as a serious problem due to increased line resistance and parasitic capacitance according as a drive frequency is increased.
Therefore, in order to solve the problem of the drive signal delay, it is tried to use copper (Cu) (bulk resistivity: 1.7 &mgr;&OHgr;·cm) having a smaller electric resistance for the interconnecting material in place of the conventional interconnecting material of Al (bulk resistivity: 2.7 &mgr;&OHgr;·cm), &agr;-Ta (bulk resistivity: 13.1 &mgr;&OHgr;·cm) and Mo (bulk resistivity: 5.8 &mgr;&OHgr;·cm). For example, “Low Resistance Copper Address Line For TFT-LCD” (Japan Display ′89 p.498-501) discloses the result of examination of a TFT-LCD that uses Cu as a gate electrode material. According to this reference document, there is a clear statement of the necessity of an improvement in adhesion property by providing a metal film of Ta or the like as a groundwork since a Cu film formed by the sputtering method has a degraded property of adhesion to a foundation glass substrate.
However, the Cu interconnecting line structure has the problems as follows.
That is, when forming both of a Cu film intended for a reduction in resistance and a groundwork metal Ta film intended for an improvement in the adhesion property of the Cu film by the sputtering method or the like by means of a vacuum film forming apparatus, the Cu film and the groundwork metal Ta film need individual film forming processes, and this increases the processes, leading to a cost increase. The Cu film and the groundwork Ta metal film also need individual etching processes, and this increases the processes, leading to a cost increase. Furthermore, the aforementioned Cu interconnecting line structure requires an increase in scale of the vacuum film forming apparatus and the etching apparatus in accordance with an increase in area of the display, i.e., an increase in film forming area, and this disadvantageously causes a production cost increase.
Accordingly, it is demanded to establish a Cu interconnecting line fabricating technique by a wet type plating system technique capable of forming a film at low cost without the need of any vacuum film forming apparatus.
On the other hand, Japanese Patent Laid-Open Publication No. HEI 2-83533 discloses the method of forming a Cu interconnecting line by a plating film forming technique without using any vacuum film forming process such as the sputtering method. In this case, a nickel (Ni) film and a gold (Au) film are successively formed by electroless plating on the groundwork of an ITO (Indium Tin Oxide) film, and a Cu film is further formed on them by electroless plating. With this arrangement, an electric interconnecting line having a Cu/Au/Ni laminate structure is provided.
The above-mentioned forming method is adopted because no sufficient adhesion property can be obtained when it is tried to form a Cu film by plating on a surface of an ITO film (indium tin oxide film) and because it is effective to interpose an Ni film having an excellent property of adhesion to the groundwork before forming the Cu film.
As shown in
FIG. 8
, if an electroless Cu plating film
102
is provided directly on this electroless Ni film
101
, then there occurs the problem that the so-called “blistering” defect of the separation of the Ni film
101
from the interface between the film and a groundwork ITO film
105
provided on a glass substrate
106
as a consequence of the permeation of a Cu plating solution through a pinhole
103
of the Ni film
101
tends to occur.
Accordingly, Japanese Patent Laid-Open Publication No. HEI 2-83533 adopts the method of forming an Ni film to a thickness of not smaller than 0.4 &mgr;m, thereafter forming an Au film to a thickness of not smaller than 0.1 &mgr;m on the surface of the Ni film by displacement plating and finally forming a Cu film to a thickness of not smaller than 0.8 &mgr;m by electroless plating. This method resolves the defect of blistering that occurs after Cu plating by eliminating the pinhole of the Ni film.
According to the construction of Japanese Patent Laid-Open Publication No. HEI 2-83533, the total thickness of the Cu/Au/Ni plating film inevitably becomes 1 &mgr;m or greater, as described hereinabove. According to this Japanese Patent Laid-Open Publication No. HEI 2-83533, there was no limitation on the total thickness of the plating on the precondition that the Cu/Au/Ni plating film was applied to a peripheral terminal portion of a liquid crystal display (LCD), and there was caused no problem if the total thickness of the plating film was formed to a thickness of 1 &mgr;m or greater.
However, if it is tried to apply the aforementioned Cu/Au/Ni plating film to bus lines (signal lines and scanning lines) existing inside the LCD panel of the liquid crystal display (LCD), then there occurs the trouble as follows.
That is, if the bus lines have a difference in level of not smaller than 1 &mgr;m, then the stepped portions sometimes exert a bad influence on the state of alignment of the liquid crystal layer. Furthermore, if there is a device structure in which other interconnecting lines extend across the plating interconnecting lines, then there is an increased probability of the occurrence of the disconnection of the interconnecting lines of the upper layer in the stepped portions.
Therefore, if it is tried to apply the Cu/Au/Ni plating film to the bus lines of the liquid crystal display device, then the total thickness of the plating film should preferably be restrained to a thickness of not greater than 0.5 &mgr;m. In the case of the plating interconnecting lines of the Cu/Au/Ni structure, the Cu film dominates the electric performance of the interconnecting lines, whereas the Ni film merely plays the role of securing the property of adhesion to the groundwork. Therefore, if it is tried to reduce the total thickness of the Cu/Au/Ni plating film, then it is important to reduce the thickness of the Ni film in order to maintain the electric characteristics of the interconnecting lines.
However, it is required to set the thickness of the Ni film to a value of not smaller than 0.4 &mgr;m in order to solve the defect of blistering as described hereinabove in the case of the metal lines described in the aforementioned Japanese Patent Laid-Open Publication No. 2-83533, and this has been a serious obstacle to the demand of reducing the total plating thickness.
SUMMARY OF THE INVENTION
Accordingly, it is
Chikama Yoshimasa
Hashimoto Takaharu
Izumi Yoshihiro
Kawashima Satoshi
Alexander John B.
Conlin David G.
Edwards & Angell LLP
Sharp Kabushiki Kaisha
Thomas T.
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