Content addressable memory having column redundancy

Details Content addressable memory having column redundancy Content addressable memory having column redundancy

2004-02-09

2004-10-12

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S189050, C365S200000

Reexamination Certificate

active

06804135

ABSTRACT:

FIELD OF INVENTION
This invention relates generally to column redundancy in content addressable memory devices.
DESCRIPTION OF RELATED ART
Column redundancy has been used to improve the yield of content addressable memory (CAM) devices. In U.S. Pat. No. 5,319,589, Yamagata et al disclose a column redundancy technique for a dynamic CAM device that allows a defective column of CAM cells to be replaced with a redundant column of CAM cells. Yamagata's CAM device includes a plurality of normal bit line circuits coupled to bit line pairs of corresponding columns of CAM cells, a redundancy bit line circuit coupled to a redundant bit line pair of the redundant column of CAM cells, and a switch circuit that selectively couples input/output (I/O) line pairs to the normal and redundant bit line circuits. Each column of CAM cells includes a pair of fuses that are blown to isolate defective columns from the CAM array. Similarly, the redundant column includes a pair of fuses that are blown to enable the redundant column to replace a defective column.
Yamagata et al's CAM device requires two fuses per column to selectively enable or disable the column. The pair of fuses required for each column undesirably increases the size of the CAM array. Further, because fuses typically do not scale well with semiconductor process technologies, the increase in array size resulting from including fuses on each column is not readily remedied by migration to a smaller geometry process technology. Thus, it would be desirable to provide a column redundancy scheme for CAM devices that is more area efficient and that scales better with new process technologies.


REFERENCES:
patent: 5319589 (1994-06-01), Yamagata et al.
patent: 6373758 (2002-04-01), Hughes et al.
patent: 6445628 (2002-09-01), Pereira et al.
patent: 6525987 (2003-02-01), Hilbert
patent: 6691252 (2004-02-01), Hughes et al.
U.S. patent application Ser. No. 10/143,051 entitled Content Addressable Memory Having Column Redundancy and filed on May 10, 2002. (Now US Patent 6,714,430).

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