Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2002-12-19
2004-11-23
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S117000, C438S120000, C438S612000
Reexamination Certificate
active
06821813
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to packaging of semiconductor integrated circuits. More particularly, the present invention relates to a new and improved process for bonding solder bumps of an IC (integrated circuit) flip chip to a substrate in semiconductor packaging technology.
BACKGROUND OF THE INVENTION
One of the last processes in the production of semiconductor integrated circuits (IC) is multi-leveled packaging, which includes expanding the electrode pitch of the IC chips containing the circuits for subsequent levels of packaging; protecting the chip from mechanical and environmental stress; providing proper thermal paths for channeling heat dissipated by the chip; and forming electronic interconnections. The manner in which the IC chips are packaged dictates the overall cost, performance, and reliability of the packaged chips, as well as of the system in which the package is applied.
Package types for IC chips can be broadly classified into two groups: hermetic-ceramic packages and plastic packages. A chip packaged in a hermetic package is isolated from the ambient environment by a vacuum-tight enclosure. The package is typically ceramic and is utilized in high-performance applications. A chip packaged in a plastic package, on the other hand, is not completely isolated from the ambient environment because the package is composed of an epoxy-based resin. Consequently, ambient air is able to penetrate the package and adversely affect the chip over time. Recent advances in plastic packaging, however, has expanded their application and performance capability. Plastic packages are cost-effective due to the fact that the production process is typically facilitated by automated batch-handling.
A recent development in the packaging of IC chips is the ball grid array (BGA) package, which may be utilized with either ceramic packages or plastic packages and involves different types of internal package structures. The BGA package uses multiple solder balls or bumps for electrical and mechanical interconnection of IC chips to other microelectronic devices. The solder bumps serve to both secure the IC chip to a circuit board and electrically interconnect the chip circuitry to a conductor pattern formed on the circuit board. The BGA technique is included under a broader connection technology known as “Controlled Collapse Chip Connection-C4” or “flip-chip” technology.
Flip chip technology can be used in conjunction with a variety of circuit board types, including ceramic substrates, printed wiring boards, flexible circuits, and silicon substrates. The solder bumps are typically located at the perimeter of the flip chip on electrically conductive bond pads that are electrically interconnected with the circuitry on the flip chip. Because of the numerous functions typically performed by the microcircuitry of a flip chip, a relatively large number of solder bumps are often required. The size of a flip chip is typically on the order of about thirteen millimeters per side, resulting in crowding of the solder bumps along the perimeter of the flip chip. Consequently, flip chip conductor patterns are typically composed of numerous individual conductors that are often spaced apart about 0.1 millimeter or less.
FIG. 1
illustrates a cross-section of a conventional flip chip
10
which is inverted and bonded to a BT substrate
20
. Formation of the flip chip
10
begins by forming multiple bonding pads
16
on the surface of a wafer substrate
12
, in electrical contact with integrated circuits (not shown) fabricated on the wafer substrate
12
. A solder bump
18
is then bonded to each of the bonding pads
16
. Each of the solder bumps
18
is typically spherical in configuration and extends through a passivation layer
14
formed on the surface of the wafer substrate
12
. A tin oxide layer
19
may coat the surface of each solder bump
18
. Finally, the flip chip
10
is subjected to a re-flow temperature of typically about 320° C. to re-flow the lead solder bumps
18
on the wafer substrate
12
, after which the flip chip
10
is inverted and the solder bumps
18
are bonded with a BT substrate
20
. The re-flow heat partially melts the tin oxide layer
19
and bonds the underlying lead solder bumps
18
to the BT substrate
20
.
Several disadvantages are inherent in the conventional process for forming the flip chip
10
in electrical contact with the BT substrate
20
. For example, in many cases the BT substrate
20
is incapable of withstanding the high reflow temperatures used to bond the solder bumps
18
to the BT substrate
20
. Furthermore, the spherical shape of the solder bumps
18
increases the likelihood of bump bridges forming between adjacent solder bumps
18
, particularly for fine bump pitch products. Accordingly, a new and improved method is needed for bonding solder bumps to a BT substrate in the packaging of IC chips.
An object of the present invention is to provide a new and improved process for packaging IC chips.
Another object of the present invention is to provide a new and improved process for bonding solder bumps of a flip chip to a BT substrate.
Yet another object of the present invention is to provide a new and improved flip chip bonding process which prevents the formation of bump bridges during the process of bonding solder bumps of a flip chip on a BT substrate in flip chip packaging.
Another object of the present invention is to provide a new and improved process for bonding solder bumps to a BT substrate in flip chip packaging technology, which process includes applying downward pressure to an inverted flip chip to generate small heat affect zones (HAZ) which provide sufficient heat to facilitate sufficient bonding of the solder bumps to the substrate.
Still another object of the present invention is to provide a new and improved process for bonding solder bumps to a BT substrate in flip chip packaging technology, which process includes applying downward pressure to an inverted flip chip in combination with ultrasonic vibration of the substrate to generate small heat affect zones (HAZ) which provide sufficient heat to facilitate sufficient bonding of the solder bumps to the substrate.
A still further object of the present invention is to provide a process for the packaging of IC chips, which process prevents overheating of BT substrates in the bonding of solder bumps to a BT substrate during flip chip packaging.
Another object of the present invention is to provide a flip chip packaging process which utilizes column-shaped solder bumps to electrically connect integrated circuits on a wafer substrate with a BT substrate in order to prevent the formation of bump bridges between the solder bumps.
Yet another object of the present invention is to provide a reliable process for bonding solder bumps on a wafer substrate to a BT substrate in a flip chip packaging process.
SUMMARY OF THE INVENTION
In accordance with these and other objects and advantages, the present invention is generally directed to a new and improved process for bonding solder bumps on an IC chip to a BT substrate in “flip chip” packaging technology. In one embodiment, the process includes forming solder bumps on an IC chip in electrical contact with integrated circuits on the chip; providing a resilient chip holder on a pressure head; retaining the backside of the chip against the bottom of the chip holder typically using vacuum pressure; and pressing the solder bumps on the chip against bond pads on the BT substrate to break the tin oxide layer on the solder bumps and bond the lead solder bumps to the BT substrate. In another embodiment, the solder bumps of the inverted IC chip are pressed against the BT substrate as the BT substrate is subjected to ultrasonic vibration. This generates friction-induced small heat affected zones (HAZ) on the substrate and enhances breaking of the tin oxide layer on the solder bumps and bonding of the solder bumps with the substrate. In each embodiment, the solder bumps may be column-shaped rather than spherical. The process avoids the use of
Nguyen Ha Tran
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
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