Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-12-21
2004-02-17
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185210, C365S189070, C365S210130, C365S207000, C365S190000, C365S233500
Reexamination Certificate
active
06693827
ABSTRACT:
RELATED APPLICATIONS
This nonprovisional application claims priority under 35 U.S.C. §119(a) on Patent Application No. 2000-80432 filed in Korea on Dec. 22, 2000, which is herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to memory devices; and, more particularly, to a memory cell sensing circuit of a nonvolatile memory device, e.g., a flash memory device, capable of enhancing its sensing speed.
2. Description of the Background Art
As a flash memory device goes to large-scale integration, its operating voltage gets progressively lower. As a result, when sensing flash memory cells, the sensing current becomes very small. Thus, a problem arises in that it is difficult to sense a memory cell through which a lot of current flows, i.e., a memory cell having a ‘1’ state.
To overcome the drawback, there has been introduced a method for increasing an output gain of a sense amplifier.
Referring to
FIG. 1
, there is shown a schematic diagram of a conventional flash memory cell sensing circuit.
A first resistor R
11
is connected between a supply voltage node Vcc and a first node Q
11
being a sensing node of a main cell M
11
. A first NMOS transistor N
11
and the main cell M
11
are positioned between the first node Q
11
, and a ground node Vss. The first NMOS transistor N
11
operates in response to an output of a first inverter I
11
inverting the potential of a bit line BL
1
of the main cell M
11
. Further, the main cell M
11
operates according to a voltage provided through a word line WL.
Meanwhile, a second resistor R
12
is attached between the supply voltage node Vcc and a second node Q
12
, being a sensing node of a reference cell M
12
. A second NMOS transistor N
12
and the reference cell M
12
are located between the second node Q
12
and the ground node Vss. The second NMOS transistor N
12
operates under the control of an output of a second inverter I
12
inverting the potential of a bit line BL
2
of the reference cell M
12
. Moreover, the reference cell M
12
operates in response to a voltage supplied through the word line WL.
A sense amplifier
11
compares the potential of the first node Q
11
being the potential of the main cell M
11
and the potential of the second node Q
12
being the potential of the reference cell M
12
, and outputs a comparison result as a sensing output signal SAOUT.
As described above, since the conventional flash memory cell sensing circuit employs a circuit for sensing a state of the main cell, and that being for sensing a state of the reference cell, whose configurations are identical to each other, the state of the main cell can be sensed by the sense amplifier comparing the potential of the main cell on the basis of the potential of the reference cell, and outputting a sensing output signal.
Hereinafter, the operation of the conventional flash memory cell sensing circuit will be explained with reference to the timing diagram illustrated in FIG.
2
.
Before a sensing enable signal SAEN having an enable state is coupled to sense a cell state, the bit line BL
1
of the main cell M
11
and the bit line BL
2
of the reference cell M
12
are precharged. That is, the supply voltage Vcc is provided to the first node Q
11
through the first resistor R
11
, and the potential of the first node Q
11
is transferred to the bit line BL
1
of the main cell M
11
through the first NMOS transistor N
11
, so as to precharge the bit line BL
1
. The first NMOS transistor N
11
is turned on since the potential of the bit line BL
1
has an initial low state and, thus, the first inverter I
11
produces an output having a high state. Then, if the potential of the bit line BL
1
becomes higher than a certain level, the first NMOS transistor N
11
is turned off in response to its input signal being inverted to a low state by the first inverter I
11
. As a result, the potential of the bit line BL
1
maintains the certain level. The bit line BL
2
of the reference cell M
12
is also precharged in the same manner as used in precharging the bit line BL
1
of the main cell M
11
.
As depicted above, after the bit line BL
1
of the main cell M
11
and the bit line BL
2
of the reference cell M
12
are precharged, if the sensing enable signal SAEN having the enable state, e.g., a high state, is inputted to the memory cell sensing circuit and a word line voltage is provided to the main cell M
11
, the sensing operation for the main cell M
11
is performed. That is to say, if the sensing enable signal SAEN of the enable state is inputted, the potential of the second node Q
12
, i.e., the potential of the reference cell M
12
, gradually decreases, and then maintains a constant potential after a prescribed time as indicated by A. In the meantime, the potential of the first node Q
11
is changed according to the state of the main cell M
11
. Namely, the potential of the bit line BL
1
maintaining the precharged potential before the sensing enable signal SAEN of the enable state is inputted, becomes lower as the word line voltage is provided to the main cell M
11
and, then, ascends again depending on the supply voltage Vcc continuously provided to the circuit, as indicated by B. Next, if the main cell M
11
has a ‘0’ state, the potential of the first node Q
11
rises as an amount of current flowing to the ground node Vss through the main cell M
11
becomes smaller. On the other hand, if the main cell M
11
has a ‘1’ state, the potential of the first node Q
11
becomes lower since the current is continuously passed to the ground node Vss through the main cell M
11
. Accordingly, the sensing output signal SAOUT of the sense amplifier
11
is changed and the state of the main cell M
11
is sensed.
In the conventional flash memory cell sensing circuit described above, in a case of the main cell having the ‘0’ state, the sensing output signal maintains its state after the sensing, without being changed. On the other hand, in a case of the main cell having the ‘1’ state, the sensing output signal is changed from the ‘0’ state in which current does not flow to the ‘1’ state as the current starts to flow. As a result, the final sensing speed of the device determined by the ‘1’ state sensing is deteriorated and, ultimately, it is inevitable for the sensing speed to be directly affected by the cell current.
Furthermore, in general, the conventional flash memory cell sensing circuit uses a resistor having a high resistance in order to improve the sensing speed. In this case, since the voltage of the sensing node is substantially low during precharging the bit line, the current cannot be provided to the bit line anymore, resulting in making the time required to precharge the bit line longer, and diminishing the sensing speed.
SUMMARY OF THE INVENTION
It is, therefore, a primary object of the present invention to provide a memory cell sensing circuit capable of enhancing a sensing speed by reducing a time required in changing a cell sensing output of a ‘0’ state to that of a ‘1’ state.
In accordance with the present invention, there is provided a memory cell sensing circuit comprising:
a main cell and a reference cell;
a first loading unit for providing a preset voltage to a sensing node of the main cell;
a second loading unit for supplying a prescribed voltage to a sensing node of the reference cell;
a first switching unit for adjusting the potential of the sensing node of the main cell;
a second switching unit for controlling the potential of the sensing node of the reference cell;
a main cell bit line voltage controlling unit for adjusting the potential of a bit line of the main cell;
a reference cell bit line voltage controlling unit for adjusting the potential of a bit line of the reference cell; and
a sense amplifier for sensing a state of the main cell by comparing the potential of the sensing node of the main cell and that of the sensing node of the reference cell.
Further scope of the applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should
Birch & Stewart Kolasch & Birch, LLP
Tran Andrew Q.
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