Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2002-11-21
2004-06-29
Jeanglaude, Jean Bruner (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S172000
Reexamination Certificate
active
06756928
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a pseudo-differential amplifier circuit including two amplifiers and an A-D (analog-to digital) converter using the pseudo-differential amplifier circuit and, more particularly, to a pipeline A-D converter using the pseudo-differential amplifier.
2. Description of the Related Art
A pipeline A-D converter using a differential amplifier circuit is publicly known. An example of the differential amplifier circuit is shown in FIG.
10
. In the differential amplifier circuit
100
in
FIG. 10
, a predetermined voltage V
p
1 is applied to the gate of each PMOS transistor MP
1
, and a predetermined voltage V
n
1 is applied to the gate of an NMOS transistor MN
4
. Each gate of two NMOS transistors MN
3
that make up a differential pair is an input terminal to the differential amplifier circuit
100
, and two input voltages ViA and ViB are respectively input to the input terminals.
Further, each junction between PMOS transistors MP
2
and NMOS transistors MN
2
is an output terminal of the differential amplifier circuit
100
, and output voltages VoA and VoB are respectively output from the output terminals. The output signal of a common-mode feedback circuit CMFB is input to the gate of each NMOS transistor MN
1
, and the output voltages VoA and VoB are adjusted thereby.
Here, let lo denote the current flowing through the NMOS transistors MN
3
that make up a differential pair. Then, a source current Io/4 flows through each of the inverter amplifiers A
1
and A
2
that form a feedback circuit. The current Io flows through each series-connected circuit consisting of PMOS transistor MP
2
and NMOS transistors MN
2
and MN
1
. Two switches SW
1
and SW
2
are turned on, to form conductive states, when a signal input to the A-D converter is sampled. When the signal input to the A-D converter is held, both switches are turned off, to form cut-off states.
In recent years, as communication speed in mobile communications and the Internet has become high, the resolution and quality of images in video apparatus have become high, and the speed in disk media have become high, demand for high performance A-D converters has been accelerated. In particular, A-D converters that achieve high speed and high precision at low voltage and low power consumption by using CMOS have been desired.
However, the differential amplifier circuit
100
shown in
FIG. 10
is a complete differential type and requires a large amount of bias current for desired output current. Therefore, such a differential amplifier circuit is inefficient with high power consumption, so that it has been disqualified for achieving reduction of power consumption in an A-D converter. Further, the differential amplifier circuit
100
of complete differential type has multi-stages of transistors connected in series between a source voltage and the ground, so that operation at low voltage is limited. Therefore, it has also been disqualified for reduction of voltage in an A-D converter.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above problems. Its first object is thus to provide a pseudo-differential amplifier circuit that achieves low power consumption by composing a pseudo differential amplifier circuit using two cascade amplifiers in place of a differential amplifier circuit and also operates at low voltage.
Further, the second object of the present invention is to provide an A-D converter that uses the above pseudo-differential amplifier circuit.
According to an aspect of the present invention, a pseudo-differential amplifier circuit includes a first amplifier that amplifies and outputs a first input signal, a second amplifier that amplifies and outputs a second input signal, which has the opposite signal level of the first input signal. The above first and second amplifiers are of the same circuit configuration, have the same characteristics, each operable to pseudo-amplify and output one of the pair of input first and second signals.
According to the present invention, a pseudo-differential amplifier circuit is formed, without a differential pair used, from a pair of first and second amplifiers having the same circuitry and characteristics and respectively amplifying a pair of input signals. Therefore, it is possible to obtain a circuit that has the function of differential amplification and operates at low voltage as well as low power consumption.
The pseudo-differential amplifier circuit may have first and second capacitors connected in series between the output terminals of the first and second amplifiers, third and fourth capacitors connected in series between the input terminals of the first and second amplifiers, a buffer section that conveys the voltage at the junction between the first and second capacitors to the junction between the third and fourth capacitors, and a switch section that applies a predetermined voltage to the junction between the first and second capacitors and controls the voltage, depending on input control signals. By these means, fluctuations in average value of the output voltages of the amplifiers in the pseudo-differential amplifier circuit can be prevented, so that a high-performance pseudo-differential amplifier circuit that achieves reduction of power consumption and operation at low voltage can be obtained.
Specifically, when a predetermined voltage is applied from the switch section, the first and second capacitors respectively memorize the voltage difference between the predetermined voltage and the average value of the two signals output from the first and second amplifiers. On the other hand, the third and fourth capacitors make the voltage difference applied to the amplifiers through the buffer section. Construction in this way prevents the average value of the output voltages of the amplifiers in the pseudo-differential amplifier circuit from fluctuating, and a high-performance A-D converter that can achieve low power consumption and low-voltage operation can be obtained.
An A-D converter in accordance with another aspect of the present invention is equipped with a sampling and hold circuit that samples and holds a pair of analog signals having mutually opposite voltage levels and a plurality of A-D converter circuits that A-D convert a pair of output signals output from the sampling and hold circuit and perform predetermined computation to output the results as a pair of input voltages to a next-stage A-D converter circuit. Each of these A-D converter circuits in the A-D converter has a sub-A-D converter that A-D converts a pair of input voltages, a sub-D-A converter that D-A converts the data obtained by the A-D conversion, a pair of arithmetic units that respectively perform arithmetic operations for the input pair of voltages using the voltages obtained by the sub-D-A converter, and a pseudo-differential amplifier circuit consisting of a pair of amplifiers that have the same circuitry and the same characteristics and performing pseudo-differential amplification for the voltages obtained by the arithmetic units.
In the A-D converter, a pseudo-differential amplifier circuit is used in each of the A-D converter circuits that perform A-D conversion and predetermined computation for a pair of output signals output from the sampling and hold circuit to output the results as a pair of input voltages to a next-stage A-D converter circuit. By this means, low power consumption and low-voltage operation can be achieved.
According to another aspect of the present invention, an A-D converter includes a sampling and hold circuit that samples and holds a pair of analog signals having mutually opposite voltage levels and a plurality of A-D converter circuits that A-D convert a pair of output signals output from the sampling and hold circuit and perform predetermined computation to output the results as a pair of input voltages to a next-stage A-D converter circuit. At least one of these A-D converter circuits includes a sub-A-D converter that A-D converts a pair of input voltages, a sub-D-
Kawahito Shoji
Miyazaki Daisuke
Birch & Stewart Kolasch & Birch, LLP
Jeanglaude Jean Bruner
Semiconductor Technology Academic Research Center
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