Chopper type comparator

Details Chopper type comparator Chopper type comparator

2002-06-26

2004-02-10

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

By periodic switching

C327S377000, C327S077000

Reexamination Certificate

active

06690213

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to a chopper type comparator in a CMOS structure that is used for series type A/D converters, two-step parallel type AID converters and the like. More particularly, the present invention relates to a chopper type comparator that can reduce feed through noises of analogue switches.
2. Conventional Technology
In recent years, greater integration and greater speed in memories and microprocessor LSIs are actively pursued due to the advances made in the miniaturization technology in CMOS processes. If an analog circuit can be realized by a process compatible with that employed for these logical LSIs, digital circuits and analogue circuits can be disposed in the same chip, and higher reliability, such that reduction in size and lower cost can be realized. Therefore, realization of analogue circuits by CMOS processes is indispensable not only for A/D converters and D/A converters, but also for microprocessors on analog/digital chips, communications, and digital OA equipment.
As a comparator used in A/D converters, a chopper type DC amplifier using bipolar or FET transistors have been placed in practical use in a field where a high level of accuracy is required. In particular, MOS transistors are most suitable for chopper switches because their leak current is small and they do not generate offset voltage.
Currently, a variety of chopper type comparators with CMOS structure are studied.
FIG. 12
shows one example of a chopper type comparator with CMOS structure.
The chopper type comparator with CMOS structure shown in
FIG. 12
was studied in “Analysis and Evaluation of CMOS Chopper Type Comparators” in Vol. J67-C, No. 5 (1984) of the Journal of the Institute of Electronics and Communication Engineers.
The chopper type comparator includes an input switching circuit
101
for switching between an input voltage V
IN
and a reference voltage V
RF
, a capacitor C
1
that connects to the input switching circuit
101
, an amplification circuit
111
formed from amplifiers (CMOS inverters)
112
in several stages, and a compensation circuit
121
.
The input switching circuit
101
is provided with a switch CT
1
for turning on and off the input voltage V
IN
, and a switch CT
2
for turning on and off the reference voltage V
RF
. Each of the switches CT
1
and CT
2
is a semiconductor element such as a MOS field effect transistor. Gate terminals are shown in the figure at upper section and lower section of the respective switches CT
1
and CT
2
. Control driver circuits
102
and
103
are connected to the gate terminals, respectively, in which control signals CK
s
, and CK
c
are inputted, respectively. The switches CT
1
and CT
2
are controlled to turn on and off by the control signals CK
s
and CK
c
, respectively.
The amplification circuit
111
comprises a CMOS inverter
112
. A switch CT
3
that is formed from a semiconductor element such as a MOS field effect transistor is disposed in a manner to couple an input side and an output side of the CMOS inverter
112
. The CMOS inverter
112
connects to a control driver circuit
113
, which provides an input of a control signal CK
b
. The switch CT
3
is controlled to turn on and off by the control signal CK
b
.
It is noted that the compensation circuit
121
is provided to lower an offset voltage that may be caused by the field through between the gate and the drain of the switch CT
3
. If the switch CT
3
is composed of a CMOS switch, self-compensation of charges by the PMOS and NMOS can be expected, and therefore the compensation circuit
121
is not necessary.
Next, a method for comparison and judgment by the chopper type comparator will be described.
FIG. 13
shows a chart to describe a method for comparison and judgment by the chopper type comparator.
Referring to
FIG. 13
, first, the switches CT
1
and CT
3
are turned on (Step
101
). Then, a voltage on an input side of the capacitor C
1
becomes an input voltage V
IN
, and a voltage on an output side thereof becomes a voltage V
B
, such that the capacitor C
1
is charged with their difference voltage (V
IN
−V
B
). Here, the voltage V
B
is a logical threshold voltage of the CMOS inverter
112
, and its period is called a sampling period (T
S
).
Next, the switch CT
3
is turned off (Step
102
), and the switch CT
1
is turned off (Step
103
) in succession.
In this instance, the switch CT
2
is turned on (Step
104
), and the input voltage V
IN
and the reference voltage V
RF
are compared, whose period is called a comparison period (T
C
).
FIG. 14
shows a timing chart indicating the above described comparison and judgment.
FIG. 14
shows a timing chart of a control signal CLK that controls the comparator shown in
FIG. 12
, and the control signals CK
s
, CK
b
, CK
c
that are inputted in the respective switches. Referring to
FIG. 14
, when the control signal CLK becomes LOW (T
PWL
), the switch CT
2
is turned off 6 ns thereafter, and switches CT
1
and CT
3
are turned on 48 ns thereafter. As the switch CT
1
is turned on, a sampling is conducted for a period T
S
.
When the control signal CLK becomes HIGH (T
HIGH
), the switch CT
3
is turned off 18 ns thereafter, and the switch CT
1
is turned off 36 ns thereafter. As the switch CT
1
is turned off, the sampling ends.
34 ns after the end of the sampling, the switch CT
2
is turned on, and a comparison is conducted for the period T
C
.
In the chopper type comparator described above, charge noise Q is generated when the switch CT
1
is turned off. The charge noise Q is called a field through noise. When the charge noised Q is generated, a voltage change of dV
1
=dQ
1
/C
1
occurs, such that the CMOS inverter
112
responds thereto, and starts providing an output.
Also, as shown in
FIG. 12
, two inverters are used in each of the control driver circuits
102
and
103
. A control signal is inputted in one of the gate terminals of each of the switches CT
1
and CT
2
through one inverter, and a control signal is inputted in the other of the gate terminals of each of the switches CT
1
and CT
2
through two inverters. As a result, a delay for one inverter stage is generated between the control signals that drive the Pch and Nch transistors in the switches CT
1
and CT
2
, such that the Pch and Nch transistors cannot be simultaneously turned on and off, and the above-described field through noise is increased.
Also, when the capacity of the capacitor C
1
is increased to suppress the value dV
1
to a smaller value, a response to the value dV
1
may not be completely returned within the comparison period, even when the switches CT
1
and CT
2
are switched at a high speed to operate the comparator at high speed. In order to return this lengthy response of the CMOS inverter and amplify the (V
IN
−V
B
) voltage, the response speed of the CMOS inverter must be increased, which leads to an increase in its power consumption. Furthermore, the use of a chopper type comparator with a larger capacitor C
1
in an A/D converter causes to lower the input band of the A/D converter, which causes to impede its high-speed operation.
The present invention has been made in view of the problems discussed above, and its object is to provide a chopper type comparator with an improved driver structure for controlling switches, which can reduce field through noise of analogue switches and which is highly effective.
SUMMARY OF THE INVENTION
To solve the problems described above, a chopper type comparator in accordance with the present invention comprises: a first switch device composed of a PMOS transistor and an NMOS transistor for switching voltage to be compared; a second switch device composed of a PMOS transistor and an NMOS transistor for switching reference voltage; a capacitor connected to an output side of both of the switch devices for storing a charge according to the voltage; an amplification inverter that is connected to an output side of the capacitor and amplifies a capacitor output signal of the capacitor; a first control driver

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