Television – Camera – system and detail – Combined image signal generator and general image signal...
Reexamination Certificate
2001-02-26
2004-10-05
Moe, Aung (Department: 2612)
Television
Camera, system and detail
Combined image signal generator and general image signal...
C348S308000
Reexamination Certificate
active
06801255
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor solid-state image pickup device having pixels two-dimensionally arrayed on a single semiconductor substrate, and an image pickup apparatus using the semiconductor solid-state image pickup device.
2. Related Background Art
In recent image input devices such as a digital still camera and digital video camera, the number of pixels of a sensor formed from a photoelectric conversion element is increasing to obtain a high quality-image. Demands have thus arisen for small pixel size and short read-out time. To meet these demands, a method of dividing a pixel signal in accordance with a plurality of read-out channels and reading out the signals has been developed.
This conventional method will be described with reference to
FIGS. 1 and 2
.
FIG. 1
is a circuit diagram showing a schematic arrangement according to the conventional method. In
FIG. 1
, each of two-dimensionally arrayed pixels
101
generates an electrical signal, e.g., so-called pixel signal corresponding to the incident light quantity. This pixel signal is read out by selecting one row by a vertical scanning circuit
102
, reading out signals of odd-numbered pixels on the row to a line memory circuit
104
, and reading out signals of even-numbered pixels on the row to a line memory circuit
109
.
A horizontal scanning circuit
105
sequentially selects pixel signals read out to the line memory circuit
104
in accordance with a horizontal shift pulse
122
externally or internally input in the chip. The selected pixel signals are amplified by an amplifier
107
, and output via an output
108
. A horizontal scanning circuit
110
sequentially selects pixel signals read out to the line memory circuit
109
in accordance with a horizontal shift pulse
123
externally or internally input in the chip. The selected pixel signals are amplified by an amplifier
112
, and output via an output
113
.
One terminal of a switch
116
is connected to the terminal of the output
108
, whereas one terminal of a switch
117
is connected to the terminal of the output
113
. The other terminal of the switch
116
is connected to that of the switch
117
. The switches
116
and
117
are alternately selected to output, from an output
120
, pixel signals arranged in a time series by combining odd- and even-numbered lines.
The two-dimensionally arrayed pixels
101
include OB (Optical Black) pixels shielded from light by a light-shielding layer or the like, and effective pixels not covered by any light-shielded layer. A dark-level signal output from an OB pixel to the output
108
is clamped to a desired potential using a clamp unit
124
, and a dark-level signal output from an OB pixel to the output
113
is clamped to a desired potential using a clamp unit
125
. If the potentials clamped by the respective clamp units are the same, an output signal from which an offset is removed can be obtained from the output
120
.
FIG. 2
is a timing chart at the seven nodes of the horizontal shift pulse
122
, horizontal shift pulse
123
, output
108
, output
113
, switch
116
, switch
117
, and output
120
.
FIG. 2
shows clamp periods
1
and
2
during which clamp operation is done.
FIG. 2
shows six clocks of each of the horizontal shift pulses
122
and
123
respectively input to the horizontal scanning circuits
105
and
110
. Timings corresponding to pixel signals of pixels from the first row to the 12th row are assigned a to l. The pixel signals a to f are dark-level signals obtained from OB pixels, and g to l are pixel signals obtained from effective pixels.
As shown in
FIG. 2
, the pixel signals a, c, e, g, i, and k synchronized with the horizontal shift pulse
122
are sequentially output to the output
108
, and the pixel signals b, d, f, h, j, and l synchronized with the horizontal shift pulse
123
are sequentially output to the output
113
. When the outputs
108
and
113
output dark-level signals, the clamp units
124
and
125
operate to clamp the dark-level signals to desired potentials. Then, the switches
116
and
117
are alternately selected to output the pixel signals a, b, c, d, e, f, g, h, i, j, k, and l to the output
120
in the order named.
As is apparent from
FIG. 2
, the clock rates of the outputs
108
and
113
suffice to be ½ that of the output
120
, and the read-out time can be relatively easily shortened. With a plurality of read-out channels, the line memory circuit is connected at a pitch corresponding to two pixels. In reducing the pixel size, pixels can be easily wired to the line memory circuit. The clamp units
124
and
125
can remove offsets for respective read-out channels, and a high-quality image signal can be attained.
As described above, a conventional pixel signal is divided in accordance with a plurality of read-out channels, offsets of the read-out channels are removed by clamping dark-level signals among pixel signals, and output signals for the respective read-out channels are sequentially selected and output in time series. This method, however, requires OB pixels as a means for clamping offsets, and this increases the layout, The clamp period increases the read-out time. In addition, this method suffers variations in clamp level due to variations in dark level caused by defective OB pixels, stray light, or the like.
SUMMARY OF THE INVENTION
It is an object of the present invention to obtain a high-quality image by accurately removing an offset generated between a plurality of channels.
To achieve the above object, according to an aspect of the present invention, there is provided an image pickup apparatus comprising two-dimensionally arrayed pixels, a plurality of read-out channels each including a read-out circuit adapted to read out signals from the pixels and an amplifier circuit, a parallel-serial conversion circuit adapted to sequentially select pixel signals output via the plurality of read-out channels and output a series of pixel signals, and a clamp unit adapted to clamp a reset level included in an output signal from the read-out circuit in order to remove an offset generated in each read-out channel.
According to another aspect of the present invention, there is provided an image pickup apparatus comprising two-dimensionally arrayed pixels, a plurality of read-out channels each including a line memory circuit adapted to hold signals from pixels of one line and an amplifier circuit, a vertical scanning circuit adapted to divide and transfer signals from the plurality of pixels to the line memory circuits, a plurality of horizontal scanning circuits adapted to output signals from the line memory circuits via corresponding amplifier circuits, a parallel-serial conversion circuit adapted to sequentially select pixel signals output from the plurality of read-out channels and output a series of pixel signals, and a clamp unit adapted to clamp a reset level included in an output signal from each read-out channel in order to remove an offset generated in each read-out channel.
These arrangements can attain the following technological advantages.
(1) No OB pixel needs to be used.
(2) A period necessary for the clamp unit can be shortened.
(3) A stable clamp level can be supplied against variations in dark level caused by defective OB pixels, stray light, or the like, and a noise component can be effectively removed.
The above and other objects and features of the present invention will be apparent from the following description in conjunction with the accompanying drawings.
REFERENCES:
patent: 5998779 (1999-12-01), Kozuka
patent: 6534757 (2003-03-01), Inui et al.
patent: 2001/0030701 (2001-10-01), Hiyama et al.
patent: 2002/0051229 (2002-05-01), Eguchi et al.
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