Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With provision for cooling the housing or its contents
Reexamination Certificate
2002-12-18
2004-02-17
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With provision for cooling the housing or its contents
C257S796000
Reexamination Certificate
active
06693350
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application is based on and incorporates herein by reference Japanese Patent Applications No. 2000-305228 filed on Oct. 4, 2000 and No. 2001-385791 filed on Dec. 19, 2001.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, in which heat is released from two sides of a semiconductor chip accommodated therein.
As that kind of device, a semiconductor device shown in
FIG. 1
is proposed. As shown in
FIG. 1
, semiconductor chips
101
,
102
and couplers
103
,
113
are located between a first heat radiation plate
106
and a second heat radiation plate
105
. Each semiconductor chips
101
,
102
and corresponding coupler
103
,
113
, each semiconductor chips
101
,
102
and the second heat radiation plate
105
, and each coupler
103
,
113
and the first heat radiation plate
106
are respectively electrically connected to each other by solders
104
.
Therefore, the two semiconductor chips
101
,
102
are electrically connected in parallel using the couplers
103
,
113
and the first and second heat radiation plates
106
,
105
. Mold resin
109
is also located between the first and second heat radiation plates
106
,
105
and in contact with a coating resin film
110
, which is located on surfaces of the semiconductor chips
101
,
102
, the couplers
103
,
113
, and the first and second heat radiation plates
106
,
105
.
The semiconductor chips
101
,
102
are respectively, for example, an IGBT chip
101
, which is an insulated gate bipolar transistor, and an FWD chip
102
, which is a fly-wheel diode. Each semiconductor chip.
101
,
102
has an element formation surface
101
a
,
102
a
, or a front surface
101
a
,
102
a
and a back surface
101
b
,
102
b
, which is opposite to the front surface
101
a
,
102
a
. Each coupler
103
,
113
is located on corresponding front surface
101
a
,
102
a.
The coupler
103
located on the front surface
101
a
of the IGBT chip
101
forms a space for wirebonding a bonding wire
108
, which is described later, above the front surface
101
a
of the IGBT chip
101
. The coupler
103
located on the front surface
102
a
of the FWD chip
102
adjusts the distance between the FWD chip
102
and the first heat radiation plate
106
such that the first heat radiation plate
106
becomes substantially parallel to the second heat radiation plate
105
.
The second heat radiation plate
105
is electrically connected to the back surface
101
b
of the IGBT chip
101
, which is a collector electrode, and the back surface
102
b
of the FWD chip
102
, which is a cathode. The first heat radiation plate
106
is electrically connected to the front surface
101
a
of the IGBT chip
101
, which is an emitter electrode, and the front surface
102
a
of the FWD chip
102
, which is an anode.
The couplers
103
,
113
and the first and second heat radiation plates
106
,
105
release the heat that is generated by the semiconductor chips
101
,
102
while functioning as electric wiring for the semiconductor chips
101
,
102
. Therefore, the solders
104
need to have a relatively high electric conductance and a relatively high thermal conductance.
Although not illustrated, a gate electrode is located at a predetermined position on the front surface
101
a
of the IGBT chip
101
. The gate electrode is electrically connected to a control terminal
107
with the bonding wire
108
. The semiconductor chips
101
,
102
, the couplers
103
,
113
, the first and second heat radiation plates
106
,
105
, the control terminal
307
, and the bonding wire
108
are integrally molded with a molding resin used for forming the molding resin
109
such that a back surface
105
b
of the second heat radiation plate
105
, a front surface
106
b
of the first heat radiation plate
106
, and a portion of the control terminal
307
are exposed, as shown in FIG.
1
.
Although not illustrated, cooling members, which cool the first and second heat radiation plates
106
,
105
, are located in contact with the back surface
105
b
of the second heat radiation plate
105
and the front surface
106
a
of the first heat radiation plate
106
, so heat is efficiently released from the first and second heat radiation plates
106
,
105
.
In the semiconductor device shown in
FIG. 1
, the semiconductor chips
101
,
102
, the couplers
103
,
113
, and the heat radiation plates
106
,
105
are respectively different in thermal expansion coefficient from the molding resin
109
. Therefore, a relatively great stress is generated in the vicinity of the boundary between the molding resin
109
and each of the semiconductor chips
101
,
102
, the couplers
103
,
113
, and the heat radiation plates
106
,
105
when the semiconductor device experiences thermal cycles. When the thermally generated stress overcomes the adhesion between the molding resin
109
and any of the semiconductor chips
101
,
102
, the couplers
103
,
113
, and the heat radiation plates
106
,
105
, the molding resin
109
peels off. The greater the difference in temperature of the thermal cycles, the smaller the number of the cycles that cause the peeling.
A stress is also generated in each solder
104
during the thermal cycles due to the difference in thermal expansion coefficient between the semiconductor chips
101
,
102
, the couplers
103
,
113
, and the heat radiation plates
106
,
105
. However, the stress in each solder
104
is suppressed by the molding resin
109
because the molding resin
109
restrains the thermal expansions of the semiconductor chips
101
,
102
, the couplers
103
,
113
, and the heat radiation plates
106
,
105
. Therefore, if the coating resin film
110
did not exist and the molding resin
109
peeled off any of the semiconductor chips
101
,
102
, the couplers
103
,
113
, and the heat radiation plates
106
,
105
, the stress in each solder
104
would increase and the solders
104
would deteriorate at an undesirably high rate. As a result, any solder
104
would crack, and the electric resistance of the solder
104
would increase.
The coating resin film
110
has a relatively high adhesion with the molding resin
109
and any of the semiconductor chips
101
,
102
, the couplers
103
,
113
, and the heat radiation plates
106
,
105
, so the molding resin
109
is prevented from peeling off during the thermal cycles.
Nevertheless, in the manufacturing process of the semiconductor device shown in
FIG. 1
, the solders
104
spread and adhere to any side surface of the semiconductor chips
101
,
102
and the couplers
103
,
113
, as illustrated in FIG.
2
. In that case, a portion of the solders
104
, which is mechanically relatively weak, exists between the side surface and the coating resin film
110
. If the semiconductor device having the portion of the solders
104
between the side surface and the coating resin film
110
experiences thermal cycles, the portion of the solders
104
peels off the side surface.
In other words, the molding resin
109
is disconnected from the side surface. In that case, as described above, the stress in that solder
104
increases and that solder
104
deteriorates at an undesirably high rate. In addition, in the case that two types of solders, which have a different melting point from each other, are used, the solders might be mixed with each other, and as a result, eutectic solder having a melting point much lower than those of the two types of solders might be formed to fuse at the temperature for the molding using the molding resin
109
.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above aspects with an object to provide a semiconductor device in which a molding resin is prevented from peeling off to assure the durablity in its electric performance.
In the present invention, a semiconductor device includes a first conductive member, a second conductive member, a semiconductor chip, which is located between the conductive members, a bonding member, which is located between the first conduct
Fukuda Yutaka
Makino Tomoatsu
Mamitsu Kuniaki
Nakase Yoshimi
Teshima Takanori
Denso Corporation
Posz & Bethards, PLC
Potter Roy
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