Pulse or digital communications – Receivers – Particular pulse demodulator or detector
Reexamination Certificate
2001-08-28
2004-10-19
Ghebretinsae, Temesghen (Department: 2631)
Pulse or digital communications
Receivers
Particular pulse demodulator or detector
C375S262000, C714S746000, C714S794000
Reexamination Certificate
active
06807239
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a soft-in, soft-out decoder used in an iterative error correction decoder which uses extrinsic information (prior probability information) to iteratively decode two or more code sequences.
2. Description of the Background Art
As one of error correction coding, an iterative error correction decoding method, called turbo coding, is known. This coding method creates a non-interleaved data sequence and an interleaved data sequence from a data sequence to be coded and uses a parallel concatenated convolutional code (PCCC) to convolute each of these data sequences. For example, “Effect of Application of Turbo Coding to W-CDMA”, by A. Fujiwara et al. (The Institute of Electronics, Information and Communication Engineers, Technical Report of TEICE, SST77-78, pp. 19-24 (December, 1997) contains an example of turbo encoder. In the decoding process of such turbo codes, two or more code sequences are sequentially and iteratively decoded. The use of the result of other decoding as the prior probability information allows the turbo coding to provide the high-performance error correction code that reaches very close to Shannon limits. During each decoding, SISO (Soft In Soft Out) decoding such as MAP (maximum a posteriori) decoding is used. In this case, extrinsic information (prior probability information) output from each decoder is stored in a memory for all data of each decode frame.
However, the problem with the turbo coding described above is that, though very high performance error correction is attained, the decoder becomes complex in configuration, requires a large amount of memory, and consumes much power. To solve this problem, the log MAP decoding which converts MAP decoding calculation to the equivalent logarithm calculation is proposed as a practical algorithm. In addition, sub-log MAP, a simplified version of log MAP, is proposed to reduce the log MAP calculation amount and the circuit size. On the other hand, SOVA (Soft Output Viterbi Algorithm), an improved version of the Viterbi algorithm, is proposed. However, the problem is that the performance of SOVA is lower than that of MAP decoding or log-MAP decoding.
The amount of memory for storing decoded prior probability information is proportional to the size of an encoded frame. This means that packet communication in which large-sized packets are transmitted requires a large amount of memory. CDMA (Code Division Multiple Access) communication, in which the dynamic range of the bit width of a signal demodulated by the demodulator is very wide, requires a still larger amount of memory. To prevent the memory amount from being increased, the bit width of this signal must be limited. However, the bit width smaller than a predetermined width degrades demodulation performance.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an iterative error correction decoder which removes the drawback of the prior art and reduces the memory amount without degrading decoding performance.
To solve the problems described above, the decoder according to the present invention comprises a plurality of metric calculators each generating a forward state metric and a backward state metric of a predetermined state for each data bit of each encoded frame; an extrinsic information calculator generating extrinsic information based on the forward state metric and the backward state metric; and a memory in which the forward state metric and the backward state metric are stored, wherein each of the plurality of metric calculators comprises a first adder generating a branch metric when the data bit is 1, based on received data, coded data, and prior probability information, and adding the state metric, which is supplied from the memory, to the branch metric to generate an addition value; a second adder generating a branch metric when the data bit is 0, based on the received data, coded data, and prior probability information, and adding the state metric, which is supplied from the memory, to the branch metric to generate an addition value; and a first maximum value selector selecting the larger of the addition value generated by the first adder and the addition value generated by the second adder to generate the state metric, wherein the extrinsic information calculator comprises a second maximum value selector adding the state metric, supplied from the memory, to each addition value generated when the forward state metric or the backward state metric, whichever is generated later, is generated by the first adder of each of the plurality of metric calculators, and selecting a largest addition value to generate a likelihood when the data bit is 1; a third maximum value selector adding the state metric, supplied from the memory, to each addition value generated when the forward state metric or the backward state metric, whichever is generated later, is generated by the second adder of each of the plurality of metric calculators, and selecting a largest addition value to generate a likelihood when the data bit is 0; a first subtracter subtracting the likelihood generated by the third maximum value selector from the likelihood generated by the second maximum value selector to generate a likelihood ratio; a second subtracter subtracting the data and the prior probability information from the likelihood ratio generated by the first subtracter; and a re-normalizer multiplying the extrinsic information generated by the second subtracter by a re-normalization coefficient to normalize the extrinsic information, and wherein the memory temporarily stores therein the state metrics calculated by the plurality of metric calculators, reads the state metric of each state metric therefrom when the state metric of a next data bit is generated, outputs the state metric to the first adder and the second adder of a predetermined metric calculator and, at the same time, stores the forward state metric or the backward state metric which is generated by each of the plurality of metric calculators and whichever is generated earlier and outputs the state metric to the second maximum value selector and the third maximum value selector of the extrinsic information calculator.
In addition, the decoder according to the present invention comprises a plurality of metric calculators each generating a forward state metric and a backward state metric of a predetermined state for each data bit of each encoded frame; an extrinsic information calculator generating extrinsic information based on the forward state metric and the backward state metric; and a memory in which the forward state metric and the backward state metric are accumulated, wherein each of the plurality of metric calculators comprises a first adder generating a branch metric when the data bit is 1, based on received data, coded data, and prior probability information, and adding the state metric, which is supplied from the memory, to the branch metric to generate an addition value; a second adder generating a branch metric when the data bit is 0, based on the received data, coded data, and prior probability information, and adding the state metric, which is supplied from the memory, to the branch metric to generate an addition value; and a first maximum value selector selecting the larger of the addition value generated by the first adder and the addition value generated by the second adder to generate the state metric, wherein the extrinsic information calculator comprises: a second maximum value selector adding the state metric, supplied from the memory, to each addition value generated when the forward state metric or the backward state metric, whichever is generated later, is generated by the first adder of each of the plurality of metric calculators, and selecting a largest addition value to generate a likelihood when the data bit is 1; a third maximum value selector adding the state metric, supplied from the memory, to each addition value generated when the forward state metric or the backward state me
Sugimoto Hiroki
Tan Kai Ren
Wang Tingwu
Xie Ping
Ghebretinsae Temesghen
Oki Techno Centre (Singapore) PTE Ltd.
Ostrolenk Faber Gerb & Soffen, LLP
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