Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2003-03-19
2004-10-05
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S209000
Reexamination Certificate
active
06800919
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-372382, filed Dec. 24, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a redundancy function.
2. Description of the Related Art
There has been known a so-called system LSI (Large-Scale Integrated Circuit), which integrates memory and logic circuits into one semiconductor chip so that one system can be formed. In the system LSI, a plurality of functional blocks (core or macro) such as a memory circuit and a logic circuit is provided on a semiconductor chip.
In a memory device or block, there has been known a defect recovery method using a redundancy circuit. More specifically, a redundancy memory cell is provided in addition to a memory cell array, and is used in place of a memory cell, which becomes defective due to a defect generated in the manufacturing process.
FIG. 7
is a view schematically showing a conventional semiconductor device having a memory macro including a redundancy function. As seen from
FIG. 7
, a redundancy cell or redundancy memory line RC is provided in a memory block MB included in a semiconductor chip C.
When making the operation test of the semiconductor device, an internal circuit is programmed using a program interconnection section P comprising a plurality of fuses or the like. The above internal circuit makes the following operation. That is, when the semiconductor device is actually used, even if the address of a defective memory cell or line including a memory cell is input, selection is switched into the redundancy memory cell RC.
A fuse has a metal interconnection line such as copper. Laser cuts the metal interconnection line, via an opening formed in the fuse, and thereby, an internal circuit is programmed. Cut or non-cut information of the fuse is stored in a latch PL. When a redundancy function operates, reference to the above information is made, and thereby, access is switched from the defective memory cell to the redundancy memory cell RC.
The fuse of the program interconnection P and the latch PL are fixed in the memory block MB, and often formed along the surroundings of the memory block MB as shown in FIG.
7
. For this reason, an interconnection line L
1
connecting the memory block MB and a functional circuit block B such as a logic circuit passes above the fuse. However, as described above, the metal interconnection line included in the fuse is exposed via the opening. As a result, the above interconnection line L
1
passes above the fuse, and thereby, this is a factor causing a short circuit.
BRIEF SUMMARY OF THE INVENTION
According to a first aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a first, second and third functional areas parted each other by a boundary region on the semiconductor substrate; a memory block formed in the first functional area, and including a plurality of memory cells recording information and a redundancy memory cell, the memory cell being substituted for at least one memory cell of the plurality of memory cells and recording information in place of the memory cell; a functional circuit block formed in the second functional area, and connected with the memory block via an interconnection line; a program interconnection block formed in the third functional area, the program interconnection block being provided on the substrate so that it does not overlap with the interconnection line on a plane of the substrate and including a program interconnection section which forms a program forming a signal path so that a defective memory cell can be substituted by the redundancy memory cell; and a data transfer section extending over from the program interconnection block to the memory block, and transferring program information relevant to the program of the program interconnection section to the memory block.
According to a second aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; first to n+2-th (n: integer of 2 or more) functional areas parted each other by a boundary region on the semiconductor substrate; first to n-th memory blocks formed in the first to n-th functional areas, respectively, and each of the first to n-th memory blocks including a plurality of memory cells recording information, and a redundancy memory cell substituted for at least one memory cell and recording information in place of the memory cell; a functional circuit block formed in the n+1-th functional area, and connected with the first to n-th memory blocks via an interconnection line; a program interconnection block formed in the n+2-th functional area so that it does not overlap with the interconnection line on a plane of the substrate and including a program interconnection section which forms a program forming a signal path so that a defective memory cell can be substituted by the redundancy memory cell; a first data transfer section extending over from the program interconnection block to the first memory block, and transferring program information relevant to the program of the program interconnection section to the first memory block; and second to n-th data transfer sections respectively extending over from i-th (i: natural number) memory block to i+1-th memory block, and respectively transferring program information of the i-th memory block to the i+1-th memory block.
According to a third aspect of the present invention, there is provided a semiconductor device comprising: a memory block provided on a first semiconductor substrate, and including a plurality of memory cells recording information and a redundancy memory cell, the memory cell being substituted for at least one memory cell of the plurality memory cells and recording information in place of the memory cell; a program interconnection block provided on a second semiconductor substrate, and including a program interconnection section which forms a program forming a signal path so that a defective memory cell can be substituted by the redundancy memory cell; and a data transfer section extending over from the program interconnection block to the memory block, and transferring program information relevant to the program of the program interconnection section to the memory block.
REFERENCES:
patent: 5394536 (1995-02-01), Coghlan et al.
patent: 5784705 (1998-07-01), Leung
patent: 5787043 (1998-07-01), Akioka et al.
patent: 2002/0167849 (2002-11-01), Ohbayashi et al.
Michael R. Ouellette, et al., “Shared Fuse Macro for Multiple Embedded Memory Devices With Redundancy”, Proceedings of the IEEE Custom Integrated Circuits Conference, 2001, 4 pages.
Hojo Takehiko
Tokushige Kaoru
Kabushiki Kaisha Toshiba
Nelms David
Nguyen Thinh T
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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