Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2000-03-10
2004-11-09
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S143000, C341S144000
Reexamination Certificate
active
06816100
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally concerns improvements to flash Analog-to-Digital Converters (ADCs), such as may be used within delta-sigma (&Dgr;&Sgr;) modulators.
The present invention particularly concerns differential input flash ADCs appropriate for integrated circuit implementation.
2. Description of the Prior Art
2.1 General Background
For mixed-signal ICs with high digital circuit content, single-poly CMOS integrated circuit processes optimized for digital circuits can presently (circa 2000) provide the lowest overall implementation cost. For example, it is preferable to avoid the expense of extra process steps beyond those required for digital circuitry—such as double-poly capacitors, thick-oxide transistors for 5 V operation, or other analog process enhancements—when analog circuits such as data converters make up only a small portion of the total die area. This is often true even if the lack of analog enhancements significantly increases the area of the analog circuitry.
However, the performance that can be achieved by data converters in a digital-optimized, single-poly CMOS process may limit the extent to which this advantage can be exploited. High-resolution data converters require linear capacitors and low-noise, low-distortion amplifier circuits to implement fundamental building blocks such as sample-and-holds, integrators, and comparators. Though the specific circuits and performance specifications are determined by the data converter's architecture, the lack of linear capacitors with low parasitic capacitance, and process-related supply voltage restrictions, arising in modern (circa 2000), digital-optimized, single-poly CMOS processes generally present key challenges in realizing high-performance data converters.
In a CMOS process without double-poly capacitors or other thin-oxide, linear capacitor structures, either metal interconnect layers or MOS structures must be used to implement linear capacitors. MOS capacitor structures (MOSCAPs) require special biasing to keep them in an accumulated or depleted operating region and to mitigate their inherent non-linearity. Metal interconnect (metal-metal) capacitors are inherently linear, but for a given value of capacitance, a metal-metal capacitor can require as much as 30 times the area of a double-poly capacitor. Moreover, the bottom plate capacitance of a metal-metal capacitor is comparable to the inter-plate capacitance, while the double-poly capacitor's parasitic capacitance is typically less than 50% of the inter-plate capacitance.
Process-related limitations on supply voltages to 3.3 V or less restrict signal swings in amplifiers and through analog switches. In switched-capacitor circuits, this necessitates increased sampling capacitances to achieve the target signal to thermal noise ratio. In switched-capacitor integrators, large feedback capacitances may be required to scale the output down to fit within the amplifier's output swing. Thus, the reduced headroom and increased loading complicate the task of realizing fast settling, low-distortion switched-capacitor circuits.
It might be possible to mitigate these problems through critical refinement of the analog circuits, but a strategy that would use digital processing to minimize the performance requirements of the analog circuits would seemingly make better use of the strengths of a digital-optimized CMOS process.
Multibit &Dgr;&Sgr; modulation-using mismatch-shaping DACs exemplifies this approach. By reducing the quantization noise power to be shaped out of band relative to two-level quantization, a multibit &Dgr;&Sgr; can achieve the same SINAD with a lower order &Dgr;&Sgr; modulator and a lower over-sampling ratio than can a single-bit design. The reduction in &Dgr;&Sgr; modulator order implies that fewer switched-capacitor stages are required, and the reduced over-sampling ratio relaxes the bandwidth and slew rate requirements on the integrators. The mismatch-shaping DAC in the feedback path causes static DAC mismatch errors to fall predominantly outside the signal band and significantly relaxes the matching requirements on the DAC's analog components.
See B. H. Leung, S. Sutarja, Multi-bit sigma-delta A/D converter incorporating a novel class of dynamic element matching techniques,
IEEE Trans. on Circuits and Systems
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IEEE J. Solid
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State Circuits
, vol. SC-30, no. 4, pp. 453-460, April 1995; M. J. Story, Digital to analogue converter adapted to select input sources based on a preselected algorithm once per cycle of a sampling-signal, U.S. Pat. No. 5,138,317, Aug. 11, 1992; H. Spence Jackson, Circuit and Method for Canceling Nonlinearity Error Associated with Component Value Mismatches in a Data Converter, U.S. Pat. No. 5,221,926, 11 Oct. 14, 1999 11 Jun. 22, 1993; R. T. Baird, T. S. Fiez, Improved &Dgr;&Sgr; DAC linearity using data weighted averaging, Proceedings of the
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, May, 1995; R. T. Baird, T. S. Fiez, Linearity enhancement of multi-bit &Dgr;&Sgr; A/D and D/A converters using data weighted averaging,
IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing
, vol. 42, no. 12, pp. 753-762, Dec. 1995; R. Schreier, B. Zhang, Noise-shaped multi-bit D/A converter employing unit elements,
Electronics Letters
, vol. 31, no. 20, pp. 1712-1713, Sept. 28, 1995; R. W. Adams, T. W. Kwan, Data-directed Scrambler for Multi-bit Noise Shaping D/A Converters, U.S. Pat. No. 5,404,142, Apr. 4, 1995; T. W. Kwan, R. W. Adams, R. Libert, A stereo multi-bit S? D/A with asynchronous master-clock interface,
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IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
, vol. 44, no. 10, pp. 808-817, Oct. 1997; and I. Galton, Spectral Shaping of Circuit Errors in Digital-to-Analog Converters, U.S. Pat. No. 5,684,482, Nov. 4, 1997.
The multibit approach eases the design requirements on the switched-capacitor circuits, but it also introduces several new design challenges. The transfer function from the first integrator input to the &Dgr;&Sgr; modulator output provides no noise shaping. Therefore, the first stage feedback DAC must have the same signal-band precision as the overall data converter. Furthermore, the reduced &Dgr;&Sgr; modulator order and over-sampling ratio imply that the noise transfer function provides less attenuation of circuit noise and distortion in the flash ADC quantizer relative to single-bit designs. Thus the flash ADC must provide sufficient common mode noise rejection and SFDR performance to meet the overall data converter's performance targets.
SUMMARY OF THE INVENTION
The present invention contemplates improvements to conventional so-called flash analog-to-digital converters (ADCs). Flash ADCS are used in a variety of applications, one example of which is as internal components within so-called delta-sigma (&Dgr;&Sgr;) modulator circuits for performing very precise analog-to-digital conversion.
The first improvement contemplated is to realize a differential-input flash ADC using digital common-mode rejection wherein the output sequences from two non-differential flash ADCs are (i) differenced, and (ii) further processed, in the digital domain.
The second improvement contemplated, which is realizable separately and independently of the first improvement, is to effect comparator offset dynamic element matching as a means of reducing the deleterious effects of ADC error resulting from the inevitable non-zero offset voltages of the comparators fro
Fogelman Eric
Galton Ian
Jensen Henrick T.
Fish & Richardson P.C.
Mai Lam T.
The Regents of the University of California
Tokar Michael
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