Metal deforming – By tool-couple embodying nonplanar tool-face – With complementary tool-faces
Reexamination Certificate
2000-09-27
2004-06-29
Crane, Daniel C. (Department: 3725)
Metal deforming
By tool-couple embodying nonplanar tool-face
With complementary tool-faces
C029S874000, C029S882000
Reexamination Certificate
active
06755069
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the field of metal forming, and more particularly to the forming of lead frames used in the assembly of micro electronic devices.
BRIEF DESCRIPTION OF PRIOR ART
Integrated circuit devices, having an integrated circuit chip and a lead frame which are sealed within a protective enclosure find wide use in products, among which are consumer electronics, computers, automobiles, telecommunications and military applications. A means to electrically interconnect an integrated circuit chip to circuitry external to the device frequently takes the form of a lead frame. The lead frame is formed from a highly electrically and thermally conductive material, such as copper or copper alloys. The lead frame is stamped or etched into a plurality of leads, and a central area, called a chip pad, on which the integrated circuit chip is attached. The chip is electrically connected to the leads, usually by wire bonding, and the device is encapsulated to provide mechanical and environmental protection.
Lead frames typically include a solid chip pad somewhat larger than the chip to which the integrated circuit chip is attached by an adhesive or alloy. However, currently many lead frames
101
are fabricated with a single or multiple small circular pads
102
as shown in
FIG. 1
, or simply to strips of metal where the chip is attached, and the large chip pad is eliminated. The chip pads
102
are connected to outer support rails
105
by thin etched or stamped extensions of the metal, called tie straps
106
. Support rails
105
also hold together one or more lead frames in a strip until encapsulation is completed.
Those lead frames having one or more small pads
102
as in
FIG. 1
are typically referred to as S-pad or small pad lead frames. A small, circular pad is positioned approximately mid-way from the edge of the tie strap to the center of the lead frame where the tie straps intersect
108
. The chip is positioned atop the frame and the unpatterned side of the chip attached to the pads by an adhesive. An outline of a chip position is represented by the dashed line
103
.
As shown in
FIG. 2
a
, lead frames
201
may be attached to the active patterned surface of the chip
203
, as in devices referred to as LOC or lead-on-chip, and illustrated in
FIGS. 2
a
and
2
b
. A chip is attached to a flat portion of the lead frames itself, and most often to a down-set or offset portion
209
of the frame.
Lead frames having a reduced chip pad area were developed in response to a failure mechanism in surface mount packages often referred to as “pop corning”. Moisture ingress into the plastic package is trapped between the chip and the metal chip pad, and when subjected to a rapid thermal excursion, such as solder attachment to a printed wiring board, the vapor pressure causes the plastic package to bulge and sometimes crack. This failure mechanism can be avoided by eliminating the large solid metal die pad.
In the process of lead frame down-setting a selected strip of metal is elongating in a die under pressure from either a hydraulic or electrically driven press while the support metal remains planar. The metal in two or more tie straps metal is forced downward to form angled bends and is pressed toward the center of the lead frame by using a forming punch to press the tie straps against the die surface. The more ductile metal, following the path of least resistance moves toward the center where the tie straps converge, and lacking a relief mechanism, the metal strip bows.
FIG. 3
a
is a schematic of a lead frame
301
with bowed tie strap
308
at the center where the tie straps converge. The semiconductor chip
302
is attached to the small pads
303
by adhesive
304
only at localized area owing to the non-planar attach area. The schematic in
FIG. 3
a
demonstrates a device bowed in a concave direction. Convex bowing is equally as big an issue for the assembly of semiconductor devices.
In conventional lead frames having a rigid or solid chip attach pad in the center, stress is relieved in the large pad, and bowing is much less of a problem. However, in the case of small pad frames where only small relief areas are provided, the narrow metal frequently is distorted at the location where pressure converges.
However, small or no pad lead frames are not without significant manufacturing challenges. One of the more difficult issues has been warping or distortion of the long thin tie straps which occurs during offsetting the chip mount area. Either convex or concave bowing of the tie strap and chip attach areas prevent the chip from seating correctly.
Owing to the reduced contact area for chip attachment, it is imperative that the chip attach area be planar and allow the small amount of adhesive on the pads to contact and firmly seat the chip. Losses resulting from bowed or distorted lead frames result in not only yield loss, but also present a reliability concern for both mechanical stresses on wire bonds, as well as diminished thermal transport path. A solution to this issue has been sought by the industry since the inception of small pad and no pad packaged devices.
SUMMARY OF THE INVENTION
As thinner integrated circuit packages, and consequently thinner lead frames are demanded by the industry, warping and distortion of the lead frame chip attach area has becomes a more prevalent issue. Further, the heavily favored lead frame materials are alloys of copper because of its excellent thermal conductivity and ease of processing, but the malleability and ductility of these copper alloys allows greater warping than other more rigid metallic alloys.
It is an object of this invention to provide an essentially no cost, permanent, and consistent means of eliminating bowing and distortion of lead frame tie straps resulting from the z-axis down-setting process.
It is an object of the invention to provide tooling which is common to a large family of devices, and the methodology for altering the tooling design to be applicable to many other lead frames sizes and shapes.
The chip attach area of lead frames is offset from the plane of the lead frame in order to minimize the length and looping height of bonding wires by positioning the chip surface at more nearly the same level as the lead frame bond fingers to which bond wires are attached. Offset or z-axis down-set is accomplished by positioning the stamped or etched lead frame in a press having a down-set die and a forming tool. The material to be offset is elongated by the contact and pressure from the forming tool, thereby stretching the metal and increasing its length with respect to the surrounding planar portion of the lead frame. The metal is being elongated or stretched along the surface of the forming die from opposite sides of the lead frame and converges toward the center of the lead frame. This results in the central area bowing in either a concave or convex direction, either of which is unacceptable.
The present invention provides a set of inserts to be positioned in the down-set die which have a protrusion above the die surface in the center of each tie strap. In addition, a series of protrusions are fabricated on the down-set forming punch. The insert tooling forms an indentation on the backside of the tie strap which allows the lead frame material to be pushed upward, and to move to the outer edge of the tie strap. In the same operation, protrusions on the forming punch create small lateral impressions on the top surface of the tie strap which control the flow of material being pushed toward the center of the lead frame during down-setting. Simultaneously creating small controlled indentations in the top and bottom surfaces, as well as along both the longitudinal and horizontal axis allows relief for the deformed lead frame material, and results in a flat, planar chip attach area.
REFERENCES:
patent: 4283839 (1981-08-01), Gursky
patent: 5053852 (1991-10-01), Biswas et al.
patent: 5126820 (1992-06-01), Brown
patent: 5391439 (1995-02-01), Tomita et al.
patent: 5819579 (1998-10-01), Roberts
Mann Wayne E.
Pelletier William J.
Brady III Wade James
Crane Daniel C.
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