System for pointer updating across paged memory

Details System for pointer updating across paged memory System for pointer updating across paged memory

1995-06-21

1996-04-16

Lane, Jack A.

395417, G06F 1210

Patent

active

055091318

ABSTRACT:
A method and system for updating the logical address of pointers used by a processor in a paged memory organization. A logical address associative memory provides a cache holding data about a paged segment of data words eliminating the need to fetch the data from main memory. Update index logic and insertion logic operate to update the logical address of an original pointer to indicate the logical next address of new data sought from main memory. The system is specifically designed to expedite the situation where the page referenced by the next address is different from that referenced by the original pointer's address.

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patent: 4794521 (1988-12-01), Ziegler et al.
patent: 4811206 (1989-03-01), Johnson
patent: 5053951 (1991-10-01), Nusinov et al.
patent: 5321836 (1994-06-01), Crawford et al.
Hayes, John P., "Computer Architecture and Organization," McGraw-Hill, 1978, pp. 370-375.

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