Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only
Reexamination Certificate
2002-12-11
2004-12-07
Dudek, James A. (Department: 2871)
Liquid crystal cells, elements and systems
Particular structure
Having significant detail of cell structure only
C349S152000
Reexamination Certificate
active
06829029
ABSTRACT:
This application claims the benefit of Korean Patent Application No. 2001-81562, filed on Dec. 20, 2001, which is hereby incorporated by reference for all purposes as if fully set forth herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly to a liquid crystal display panel of line on glass (LOG) type and a fabricating method thereof that is adaptive for minimizing line resistance of LOG-type patterns provided on the liquid crystal display panel.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls a light transmittance of a liquid crystal using an electric field to display a picture. To this end, the LCD includes a liquid crystal display panel having liquid crystal cells arranged in a matrix type, and a driving circuit for driving the liquid crystal display panel.
In the conventional liquid crystal display panel, gate lines and data lines are arranged in such a manner to cross each other. The liquid crystal cell is positioned at each area where the gate lines cross the data lines. The liquid crystal display panel is provided with pixel electrodes and a common electrode for applying an electric field to each of the liquid crystal cells. Each pixel electrode is connected, via the source and drain electrodes of a thin film transistor acting as a switching device, to any one of data lines. The gate electrode of the thin film transistor is connected to any one of the gate lines allowing a pixel voltage signal to be applied to the pixel electrodes for each one line.
The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for controlling the gate driver and the data driver, and a power supply for supplying various driving voltages used in the LCD. The timing controller controls a driving timing of the gate driver and the data driver and applies a pixel data signal to the data driver. The power supply, using input power, generates driving voltages such as a common voltage Vcom, a gate high voltage Vgh and a gate low voltage Vgl, etc, which are needed in the liquid crystal display. The gate driver sequentially applies a scanning signal to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal display panel one line by one line. The data driver applies a pixel voltage signal to each of the data lines whenever the scanning signal is applied to any one of the gate lines. Accordingly, the LCD controls the light transmittance by an electric field applied between the pixel electrode and the common electrode in accordance with the pixel voltage signal for each liquid crystal cell, to thereby display a picture.
The data driver and the gate driver are directly connected to the liquid crystal display panel and integrated into a plurality of integrated circuits (ICs). Each of the data drive IC and the gate drive IC are mounted in a tape carrier package (TCP) for connection to the liquid crystal display panel by a tape automated bonding (TAB) system, or mounted directly onto the liquid crystal display panel by a chip on glass (COG) system. The printed circuit board includes a data PCB and a gate PCB.
The drive ICs are connected, via the TCP, to the liquid crystal display panel by the TAB system and receive control signals and direct current voltages inputted from the exterior over signal lines formed on a printed circuit board (PCB) connected to the TCP. The drive ICs are also connected to each other. More specifically, the data drive ICs are connected, in series, via signal lines formed on the data PCB, and commonly receive control signals from the timing controller, a pixel data signal and driving voltages from the power supply. The gate drive ICs are connected, in series, via signal lines formed on the gate PCB, and commonly receive control signals from the timing controller and driving voltages from the power supply.
The drive ICs mounted onto the liquid crystal display panel by the COG system are connected to each other by a line on glass (LOG) system in which signal lines are mounted on the liquid crystal display panel, that is, on a lower glass, and receive control signals from the timing controller and driving voltages from the power supply.
Recently, even when the drive ICs are connected to the liquid crystal display panel by the TAB system, the LOG system is employed to eliminate the PCB, and permits the manufacture of a thinner liquid crystal display. Accordingly, signal lines for connection to the gate drive ICs require relatively small signal lines, are provided on the liquid crystal display panel by the LOG system and eliminate the need for the gate PCB. In other words, the gate drive ICs of TAB system are connected, in series, to each other over signal lines mounted onto the lower glass of the liquid crystal display panel, and commonly receive control signals and driving voltage signals, which are hereinafter referred to as “gate driving signals”.
For example, as shown in
FIG. 1
, the liquid crystal display omitting the gate PCB by utilizing LOG-type signal wiring includes a liquid crystal display panel
1
, a plurality of data TCPs
8
connected between the liquid crystal display panel
1
and a data PCB
12
, a plurality of gate TCPs
14
connected to other side of the liquid crystal display panel
1
, data drive ICs
10
mounted in the data TCPs
8
, and gate drive ICs
16
mounted in the gate TCPs
14
.
The liquid crystal display panel
1
includes a lower substrate
2
provided with various signal lines and a thin film transistor array, an upper substrate
4
provided with a color filter array, and a liquid crystal injected between the lower substrate
2
and the upper substrate
4
. Such a liquid crystal display panel
1
is provided with a picture display area
21
that consists of liquid crystal cells provided at intersections between gate lines
20
and data lines
18
for the purpose of displaying a picture. At the outer area of the lower substrate
2
located at the outer side of the picture display area
21
, data pads extended from the data lines
18
and gate pads extended from the gate lines
20
are positioned. Further, a LOG-type signal line group
26
for transferring gate driving signals applied to the gate drive IC
16
is positioned at the outer area of the lower substrate
2
.
The data TCP
8
supports the data drive IC
10
, and is provided with input pads
24
and output pads
25
electrically connected to the data drive IC
10
. The input pads
24
of the data TCP
8
are electrically connected to the output pads of the data PCB
12
while the output pads
25
are electrically connected to the data pads on the lower substrate
2
. Thus, the first data TCP
8
is also provided with a gate driving signal transmission group
22
electrically connected to the LOG-type signal line group
26
on the lower substrate
2
. This gate driving signal transmission group
22
applies gate driving signals from the timing controller and the power supply, via the data PCB
12
, to the LOG-type signal line group
26
.
The data drive ICs
10
convert digital pixel data signals into analog pixel voltage signals to apply them to the data lines
18
on the liquid crystal display panel.
Similarly, the gate TCP
14
is mounted with a gate drive IC
16
, and is provided with a gate driving signal transmission line group
28
electrically connected to the gate drive IC
16
and output pads
30
. The gate driving signal transmission line group
28
is electrically connected to the LOG-type signal line group
26
on the lower substrate
2
, and the output pads
30
are electrically connected to the gate pads on the lower substrate
2
.
Each gate drive ICs
16
sequentially applies a scanning signal, that is, a gate high voltage signal Vgh to a gate line
20
in response to input control signals. Further, the gate drive ICs
16
applies a gate low voltage signal Vgl to the gate line
20
in the remaining interval where the gate high voltage signal Vgh is not app
Hwang Seong Soo
Moon Su Hwan
Park Dae Lim
Dudek James A.
LG.Philips LCD Co. , Ltd.
McKenna Long & Aldridge LLP
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