Coded data generation or conversion – Analog to digital conversion followed by digital to analog...
Reexamination Certificate
2003-05-22
2004-11-02
Jeanglaude, Jean Bruner (Department: 2819)
Coded data generation or conversion
Analog to digital conversion followed by digital to analog...
C341S155000
Reexamination Certificate
active
06812874
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to methods and apparatus for processing electrical signals, and more particularly to a method and apparatus for processing an electrical signal that is in analog form.
BACKGROUND
Techniques for processing analog electrical signals are well known. Processing can occur in the analog domain using diodes, transistors, operational amplifiers, etc., or in the digital domain after the signal has been digitized or measured, by means of an analog-to-digital converter. Analog-to-digital converter (ADC) design continues to advance rapidly both in resolution, accuracy, and conversion speed. Additionally, ADC integrated circuits have been to incorporate some of the circuit functions that traditionally were packaged as separate devices.
Resolution, accuracy and speed are traded off against each other depending upon the intended use and application. A so-called FLASH type of ADC is limited to a lower resolution and accuracy by converts quite rapidly. A successive-approximation type of ADC has high resolution and accuracy but requires more time to complete the conversion. Sigma-Delta ADCs take a very long time to complete but can measure with a voltage accuracy of greater than 1 part in a million. Each of the ADC architectures has a place in the wide range of electronic systems in use today.
Analog-to-Digital converters are practically always connected to computers. Since binary coding is the usual language of digital circuitry, ADCs virtually without exception present their output in a binary code to simplify their connection to the computer's data bus. Typically the computer will read the ADC data when the computer program commands it, or the data is read continuously from the ADC and written into digital memory whereby the computer retrieves the plurality of stored data at a later time.
This output format blends well with successive-approximation ADCs since their internal architecture calculates each binary output bit from the most significant bit, one-by-one, down to the least significant bit. Binary formatting is a natural product of the successive-approximation algorithm.
A sigma-delta ADC is essentially very low-resolution converter whose output is averaged over a long period of time to arrive at a high-resolution value. The averaging is done with digital filtering techniques, which also naturally produce binary formatted data.
FLASH ADCs are the least amendable to producing a binary output and a complex encoding circuit is required to reduce the measuring circuits output into a binary code. The reduction to binary makes up a significant portion of the FLASH ADCs conversion time. They are still faster by far than the two other types.
In systems that require the fastest analog-to-digital conversion rates, the FLASH ADC is the only choice. An example of such a system is an existing amplifier system in which a radio frequency (RF) signal requires modification before application in a manner equal and opposite to the predicted unwanted distortion introduced by the power amplifier. The correction applied is a function of the RF input signal's power envelope. The power envelope is sensed by a diode detector device, which outputs a voltage that is rapidly sampled by an 8-bit FLASH ADC. Prior to outputting the digital value, the value is naturally encoded into an eight-bit binary word. This value is used to select one or more values from a digital memory. As part of this selection process, the nominally 8-bit encoded value is decoded to select the unique memory location. These values stored in memory are numerical correction coefficients. The correction coefficients selected by any particular power level are output from memory to digital-to-analog converters (DACs). The DACs output voltages modify, by various means, the original RF signal to effect the distortion reduction. Since the signal processing by the detector, analog-to-digital converter, the correction coefficient look-up, and the digital-to-analog converters take a discrete amount of time; the RF signal must be delayed by the same time interval by e.g., using an RF delay element.
The analog-to-digital converter encoding delay is typically on the order of three clock cycles. The look-up-table and the digital-to-analog converters each typically introduce an additional clock delay or two. This relatively large amount of delay is a significant cost factor in these distortion reduction circuits. The RF delay element is expensive and difficult to package. In one implementation of this circuit, the delay required can be on the order of 100 nanoseconds (ns) or longer. Furthermore, the cost of the delay element is proportional to the required delay. For example, in an implementation of an RF delay element, a shielded and tuned wave-guide is used to provide the necessary delay, which wave-guide can cost on the order of $100 per implementation depending upon the exact delay required.
In addition to the above problems caused by delays, the above-mentioned circuit requires several expensive components due to inter alia linear performance requirements. The required analog-to-digital converter, look-up-table and digital-to-analog converter typically must operate at high frequencies, for example 100-300 MHz, which nearly represents the current limit of the technology for these type of circuits (i.e., analog-to-digital converters and digital-to-analog converters) that exhibit good linear accuracy without undue cost.
FLASH analog-to-digital converters usually employ an architecture where the input voltage to be measured is compared to each tap of a resistor ladder network. The resistor ladder network divides a reference voltage into many fractional voltage steps. The reference voltage sets the range over which the input voltage can be measured. The input voltage is compared to each fractional voltage with a separate analog comparator. Analog comparators receive the two input voltages and output a digital signal, which represents a Boolean true if the input voltage, is greater than the reference voltage step at each resistor tap. The position of the boundary between the comparators indicating a Boolean true and those indicating false is encoded into the ADCs binary output code. During manufacture, the resistor ladder may not contain equal ohmic values, so the voltage steps would not be equally spaced. As linearity is a strongly desired, even expected characteristic of ADCs, the devices resistor values are laser trimmed. This trimming process adds to the device cost. The same is true for digital-to-analog converters.
The Radio Frequency (RF) detector used in this application must have a wide dynamic range. Such detectors inherently exhibit non-linear responses at the high and low ends of their frequency ranges. Wide range linear detectors are prohibitively expensive for the given application.
Similar problems exist in analog processors used in other applications. Processing speed, accuracy, and dynamic range are often sacrificed for cost purposes, and complexity must be added to the system elsewhere to accommodate these limitations.
The present invention is therefore directed to the problem of developing a method and apparatus for processing analog signals in a fast, cost-effective manner while improving speed and accuracy.
SUMMARY OF THE INVENTION
The present invention solves these and other problems by providing inter alia a method and apparatus for processing an analog signal that includes a rapid input conversion process that uses a boundary detection of logic on its output side and an input-to-output mapping process, wherein the outputs of the boundary detection of logic drive the addresses of the input-to-output mapping process. A complete conversion of the input amplitude to a binary encoded word is avoided, thereby significantly reducing throughput delay. Optionally, the above method and apparatus include a digital-to-analog conversion process depending upon the form of the desired output.
According to another aspect of the present invention, an exemplary embodiment of an a
Andrew Corporation
Fortkort, Esq. Michael P.
Jeanglaude Jean Bruner
Mayor Fortkort & Williams, PC
William, Esq. Karin L.
LandOfFree
Method and apparatus for processing analog signal does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for processing analog signal, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for processing analog signal will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3319089