Surface emitting semiconductor laser device

Details Surface emitting semiconductor laser device Surface emitting semiconductor laser device

2002-08-06

2004-12-07

Ho, Tan (Department: 2828)

Coherent light generators

Particular active media

Semiconductor

C372S046012

Reexamination Certificate

active

06829274

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a surface emitting semiconductor laser device (hereinafter referred to as surface emitting laser device) and, more particularly to a vertical-cavity surface emitting laser device that emits in a single transverse mode with excellent stability and is suited as a light source for use in the field of optical data transmission and optical communication.
2. Description of the Related Art
The surface emitting laser device, which emits laser light in a direction perpendicular to the substrate surface, attracts attention as a light source for use in the data communication field these days. One of the reasons for the attention is that a plurality of surface emitting laser devices can be arranged in a two-dimensional array on the same substrate, unlike the Fabry-Perot resonant cavity semiconductor laser device.
The surface emitting laser device has a pair of semiconductor multilayer reflectors (distributed Bragg reflector: DBR) each including Al
x
Ga
(1-x)
As/Al
y
Ga
(1-y)
As layer pairs (where x and y for the molecular ratio of GaAs and AlAs satisfy 0y<x1), which overlie a semiconductor substrate made of GaAs or InP. The surface emitting laser device has between the pair of reflectors a vertical resonant cavity including an active layer structure and emits laser light in the direction perpendicular to the substrate surface.
In particular, the GaAs-group surface emitting laser device can employ DBRs including AlGaAs layers, which well lattice match with the GaAs substrate and have an excellent thermal conductivity and a higher reflectivity, and thus is expected for use as a laser device having an emission wavelength of 0.8 &mgr;m to 1.0 &mgr;m.
There is a current confinement structure available for the surface emitting laser device, in which a narrowed current injection area is provided to increase the current efficiency and decrease the threshold current of the laser device. The current confinement structure is categorized in two types: a current confinement structure having an ion-implanted p-n junction and an oxidized-Al current confinement structure. In the oxidized-Al current confinement structure, for example, the Al component in an AlAs or AlGaAs layer is selectively oxidized to have a peripheral oxidized-Al area and a central non-oxidized area, the latter constituting the current injection area. The oxidized-Al current confinement structure has an excellent current confinement function and can be fabricated relatively easily, whereby the oxidized-Al current confinement structure is widely used in the surface emitting laser device.
FIG. 1
is a perspective view illustrating the configuration of a GaAs-group surface emitting laser device having an oxidized-Al current confinement structure.
The surface emitting laser device
10
of
FIG. 1
has a layer structure including an n-type lower DBR
14
, a vertical resonant cavity
16
, a p-type upper DBR
18
, and a 10 nm-thick p-GaAs cap layer
20
, which are deposited on an n-GaAs substrate
12
.
The n-type lower DBR
14
is formed in a multi-layer reflector structure having 35 n-type Al
0 2
Ga
0 8
As/Al
0.9
Ga
0 1
As layer pairs.
The resonant cavity
16
includes an undoped Al
0.3
Ga
0.7
As lower cladding layer
16
a
, a GaAs/Al
0.2
Ga
0 8
As multi-quantum-well (MQW) active layer structure
16
b
, and an undoped Al
0 3
Ga
0 7
As upper cladding layer
16
c.
The p-type upper DBR
18
is formed in a multi-layer reflector structure having 20.5 p-type Al
0.2
Ga
0 8
As/Al
0 9
Ga
0.1
As layer pairs, with the bottom Al
0 9
Ga
0 1
As layer being replaced by a 50 nm-thick AlAs layer
24
to implement a current confinement structure.
In addition, the p-type cap layer
20
, the p-type upper DBR
18
, the resonant cavity
16
, and the upper layers of the n-type lower DBR
14
are configured by etching to a mesa post
22
.
For the current confinements structure, the AlAs layer
24
formed as the bottom layer of the p-type upper DBR
18
is selectively oxidized with steam at a high temperature from the periphery of the mesa post
22
, thereby forming an annular oxidized-Al area
24
B. The non-oxidized central area
24
A of the AlAs layer
24
surrounded by the oxidized-Al area
24
B serves as a current injection area.
A SiNx passivation film
26
is formed on the side-wall of the mesa post
22
and the n-type lower DBR
14
outside the mesa post
22
. A polyimide layer
28
embeds the periphery of the mesa post
22
for achieving planarization, as well as for raising the thermal conductivity, reducing the parasitic capacitance, and improving the operating speed.
On top of the mesa post
22
, there is provided an annular p-side electrode
30
in electric contact with the p-GaAs cap layer
20
, whereas an n-side electrode
32
is provided on the bottom surface of the n-GaAs substrate
12
.
FIGS. 2A
to
2
F depict the conventional surface emitting laser device of
FIG. 1
during consecutive steps of fabrication thereof.
First, the n-GaAs substrate
12
is subjected to an acid treatment to clean the substrate surface, and then introduced into a MOCVD system, wherein 35 n-type Al
0.2
Ga
0.8
As/Al
0 9
Ga
0.1
As layer pairs are deposited by an epitaxial growth technique to form the n-type lower DBR
14
on the n-GaAs substrate
12
. On the bottom layer of the p-type upper DBR
18
, the 50 nm-thick AlAs film
25
is formed instead of the Al
0.9
Ga
0.1
As film.
Subsequently, the undoped Al
0 3
Ga
0 7
As cladding layer
16
a
, the GaAs/Al
0.2
Ga
0.8
As MQW active layer structure
16
b
, and the undoped Al
0 3
Ga
0.7
As cladding layer
16
c
are epitaxially deposited.
Thereafter, 20.5 p-type Al
0.2
Ga
0 8
As/Al
0.9
Ga
0.1
As layer pairs are stacked to form the p-type upper DBR
18
, followed by epitaxial growth of the p-GaAs cap layer
20
, thereby forming the layer structure as shown in FIG.
2
A.
Subsequently, using a plasma CVD system, a SiNx film
33
is deposited on the p-GaAs cap layer
20
. Further, a resist film (not shown) is deposited on the SiNx film
33
, and then patterned by photolithography to form a resist mask
34
having a diameter of about 40 &mgr;m, as shown in FIG.
2
B.
After the resist mask
34
is formed, the SiNx film
33
is etched by reactive ion etching (RIE) using a CF
4
gas as an etching gas and the resist mask
34
as an etching mask. Then, the p-type cap layer
20
, the p-type upper DBR
18
, the resonant cavity
16
, and the top portion of the n-type lower DBR
14
are etched by a reactive ion beam etching (RIBE) system using a chlorine gas as an etching gas, to form a cylindrical mesa post
22
, as shown in FIG.
2
C.
After the etching is completed, the resist mask
34
is removed. Subsequently, the layer structure shown in
FIG. 3C
is subjected to a so-called wet oxidation treatment for about 25 minutes in a steam ambient at a temperature of 400.
As shown in
FIG. 2D
, the wet oxidation treatment causes the Al component in the AlAs layer
25
on the bottom of the p-type upper DBR
18
to be oxidized into Al
2
O
3
from the outer periphery of the mesa post
22
, thereby forming the oxidized-Al area
24
B as a current confinement area at the bottom portion of the mesa post
22
.
On the other hand, the central area of the AlAs layer
24
left as the non-oxidized area
24
A serves as a current injection area. The current injection area
24
A surrounded by the oxidized-Al area
24
B is 5 &mgr;m in diameter.
After the wet oxidation treatment is completed, the SiNx film
33
is removed by RIE.
Then, as shown in
FIG. 2E
, using a plasma CVD technique, the SiNx passivation film
26
is deposited on the top and side-wall of the mesa post
22
and on the n-type lower DBR
14
outside the mesa post
22
.
The polyimide layer
28
is then formed on the SiNx passivation film
26
to bury the mesa post
22
. Subsequently, by using a photolithographic technique, a portion of the polyimide layer
28
formed on top of the mesa post
22
is removed to expose the SiNx passivation film
26
, as shown in FIG.
2
E.
Thereafter, by a RIE technique using a

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