CMOS comparator output stage and method

Details CMOS comparator output stage and method CMOS comparator output stage and method

2002-07-23

2004-11-16

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S112000, C326S085000, C326S087000

Reexamination Certificate

active

06819148

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to CMOS circuitry, and more particularly to circuitry for eliminating shoot-through currents in complementary output stages of CMOS circuitry, and still more particularly to preventing shoot-through currents during switching of output stages of CMOS comparators.
The output stages of CMOS comparators usually are designed using a complementary CMOS inverter having large pull-up transistors and large pull-down transistors. See the paper “A 1 Mv Resolution, 10 Ms/s Rail-to-Rail Comparator in 0.5 &mgr;m Low-Voltage CMOS Process”, by R. River and F. Maloberti, ISCAS-97, pages 461-464. The input voltage of the CMOS inverter changes relatively slowly during switching because the rise times and fall times thereof are limited by the amount of current which can be supplied from the previous input stage to charge and discharge the large gate capacitances of the pull-up and pull-down transistors of the CMOS inverter. Consequently, there is a relatively large amount of time during which both the pull-up transistors and the pull-down transistors are simultaneously on. This causes large “shoot-through” currents to flow from the positive voltage supply rail through the simultaneously on pull-up and pull-down transistors to the negative voltage supply rail. The large shoot-through current increases the current consumption of the CMOS comparator circuit, which is especially significant for low-power CMOS comparators being operated at high switching speeds. The large shoot-through currents also generate noise and EMI that may adversely affect other circuitry that is coupled to the CMOS comparator. Large shoot-through currents in CMOS circuits also may cause undesirable noise in power line conductors supplying power to the CMOS circuits.
Some prior art circuits utilize non-overlapping drivers circuits to drive the gates of the P-channel pull-up transistor and the N-channel pull-down transistor so as to prevent shoot-through currents, as shown in
FIG. 9
of “Analog VLSI Design of Multi-Phase Voltage Doublers with Frequency Regulation” by Fengjing Aiu, Janusz A. Starzyk and Ying-Wei Jan, 1999 Southwest Symposium on Mixed-Signal Design, pages 9-14. Other prior art circuits operate to provide a “dead time” between the switching off of one of the pull-up and pull-down transistors and the switching on of the other.
For a long time there has been an unmet need for a simple, effective, inexpensive way of preventing shoot-through current in CMOS circuitry, especially CMOS comparators.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide reduced shoot-through currents in an output stage of a CMOS comparator.
It is another object of the invention to provide reduced shoot-through currents in a CMOS circuit.
It is another object of the invention to provide reduced shoot-through currents in a CMOS power inverter circuit.
It is another object of the invention to provide reduced EMI (electromagnetic interference) in a CMOS comparator circuit.
It is another object of the invention to reduce power line noise generated by shoot-through currents in CMOS circuitry.
It is another object of the invention to reduce current consumption of CMOS switching circuitry.
It is another object of the invention to reduce EMI caused by CMOS switching circuitry.
It is another object of the invention to provide a CMOS comparator having reduced current consumption and noise caused by shoot-through currents.
Briefly described, and in accordance with one embodiment thereof, the invention provides a CMOS circuit that includes a P-channel pull-up transistor (MP) and an N-channel pull-down transistor (MN), and also includes a first feedback circuit (
6
or
13
A) producing a first delayed signal (V
7
or V
GMN
) on the gate of the pull-down transistor (MN) to turn on the pull-down transistor (MN) a first predetermined amount of time after the pull-up transistor (MP) is turned completely off, so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN). The CMOS circuit also includes a second feedback circuit (
4
or
14
A) producing a second delayed signal (V
5
or V
GMP
) on the gate of the pull-up transistor (MP) to turn on the pull-up transistor (MP) a second predetermined amount of time after the pull-down transistor (MN) is turned completely off, so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN).
In one embodiment, the invention provides a CMOS circuit including a P-channel pull-up transistor (MP) and an N-channel pull-down transistor (MN), a P-channel first transistor (M
1
) having a source coupled to a first supply voltage (V+) and a gate coupled to a first input terminal (
2
A) for receiving a first input current (I
in1
), and an N-channel second transistor (M
2
) having a source coupled to a second supply voltage (V−) and a gate coupled to a second input terminal (
2
B) for receiving a second input current (I
in2
). A P-channel third transistor (M
1
A) has a source coupled to the first supply voltage (V+), a gate coupled to the first input terminal (
2
A), and a drain coupled to a gate of the pull-up transistor (MP). An N-channel fourth transistor (M
2
A) has a source coupled to the second supply voltage (V−) and a gate coupled to the second input terminal (
2
B). A first feedback circuit (
13
A) has an input coupled to the gate of the pull-up transistor (MP) and an output coupled to a gate of a P-channel fourth transistor (M
3
) having a source coupled to a drain of the first transistor (M
1
) and a drain coupled to a gate of the pull-down transistor (MN) and a drain of the second transistor (M
2
). A second feedback circuit (
14
A) has an input coupled to the gate of the pull-down transistor (MN) and an output coupled to a gate of an N-channel sixth transistor (M
4
) having a source coupled to a drain of the fourth transistor and a drain coupled to the gate of the pull-up transistor (MP). The first feedback circuit (
13
A) produces a first delayed signal (V
13
) on the gate of the fifth transistor (M
3
) which causes the fifth transistor to turn on the pull-down transistor (MN) a first predetermined amount of time after the pull-up transistor (MP) is turned completely off, so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN). The second feedback circuit (
14
A) produces a second delayed signal (V
14
) on the gate of the sixth transistor (M
4
) which causes the sixth transistor to turn on the pull-up transistor (MP) a second predetermined amount of time after the pull-down transistor (MN) is turned completely off, so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN). In this described embodiment, the first (I
in1
) and second (I
in2
) input currents are produced by a differential folded cascode stage of a differential input stage of a CMOS comparator circuit.
In one described embodiment, the first feedback circuit (
13
A) includes a first CMOS inverter (
13
), a first current source (I
1
) coupled between the first CMOS inverter (
13
) and the second supply voltage (V−), an input coupled to the gate of the pull-up transistor (MP), and an output coupled to the gate of the fifth transistor (M
3
). The second feedback circuit (
14
A) includes a second CMOS inverter (
14
), a second current source (I
0
) coupled between the second CMOS inverter (
14
) and the first supply voltage (V+), an input coupled to the gate of the pull-down transistor (MN), and an output coupled to the gate of the sixth transistor (M
4
). In one described embodiment, the first CMOS inverter (
13
) includes a P-channel seventh transistor (MPl) having a source coupled to the first supply voltage (V+) and an N-channel eighth transistor (M
5
) having a drain coupled to the drain of the seventh transistor (MP
1
) and a source coupled to the first current source (I
1
)

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