Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Wire contact – lead – or bond
Reexamination Certificate
2001-07-24
2004-06-08
Thai, Luan (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Wire contact, lead, or bond
C257S723000, C257S724000, C257S790000, C257S777000
Reexamination Certificate
active
06747361
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and, particularly but not limited, to a bare chip and a packaging method thereof. The present application is based on Japanese Patent Application No. 225982/2000, which is incorporated herein by reference.
2. Background
Heretofore, a high-quality semiconductor chip, particularly a high-quality bare chip (hereinafter HQC) and the efficient acquisition of an HQC has recently been desired. The method of obtaining the HQC will be described hereinbelow with reference to
FIGS. 1A
to
1
C.
FIGS. 1A
to
1
C show a conventional method of screening for a HQC. As shown in
FIG. 1A
, a predetermined probe test is first made on each semiconductor chip
103
in a semiconductor wafer
101
form. Thereafter, the semiconductor wafer
101
is divided into semiconductor chips
103
as shown FIG.
1
B. Electrodes
104
are formed on the surfaces of these semiconductor chips
103
and are arranged almost on the center line of the semiconductor chip
103
or a peripheral edge portion of the semiconductor chip
103
, in most cases. Thereafter, the semiconductor chips
103
are selected based on the results of the probe test and are stored in a chip tray or carrier socket for a bum-in test. The bum-in test (to be referred to as “BT” hereinafter) is made on these chips using a HQC special jig and device. The chips which pass the test are taken out from the BT chip tray (or carrier socket), packaged and shipped.
FIG. 1C
is a sectional view of a chip, mounted on a mounting substrate, which will be used to describe a packaging procedure. Accordingly, the semiconductor chip
103
is directly mounted on the mounting substrate
102
, and the electrodes
104
on the semiconductor chip
103
are connected to the electrodes
106
on the mounting substrate with a bonding wire
105
. The semiconductor chip
103
is then sealed with a sealing resin to form a resin sealed package
107
.
When an unpackaged semiconductor chip, that is, a bare chip, is screened, as in the prior art, the semiconductor chip or semiconductor wafer is easily broken because it has a thin formation and is susceptible to damage by a socket, probe or tester used for the screening test. Therefore, the specifications of the tester become complicated and the costs of the test become high because of the need for the test to be performed very delicately. The screening test is carried out by contacting the probe to the electrode
104
of the semiconductor chip
103
. Since the electrode
104
also serves as a bonding pad for mounting the bare chip on the substrate
102
, the surface of the electrode
104
must be prevented from being scratched by the end of the probe. If the surface of the electrode
104
is scratched, the electrode bonding may peel off, and even if the semiconductor chip
103
itself is a HQC, the semiconductor package
106
is regarded as defective, thereby reducing the yield. Further, because of the semiconductor chip's exposure, the chip
103
and wafer
101
are easily affected by environmental factors, such as water and stains that result in the HQC becoming not suitable for the market.
The defective rate of semiconductor packages incorporating a single semiconductor chip, which is unscreened and not a HQC, does not pose a big problem when a screening test and a BT are made on the semiconductor chip in package form. However, in the case of a Multi Chip Package (hereinafter MCP), which is a semiconductor package incorporating a plurality of semiconductor chips, all of the semiconductor chips constituting the MCP are not always a HQC. That is, when a plurality of semiconductor chips, which are unknown as to whether they are a HQC or not, are incorporated in a single semiconductor package, the defective rate may become large due to the multiplication of semiconductor chips, which have the potential to be defective, thereby reducing the yield of the MCP.
It is an object of the present invention to provide a semiconductor chip and device, which is capable of being easily tested for a HQC status and which can retain its quality without being affected by the surrounding environment, and a packaging method thereof.
SUMMARY OF THE INVENTION
A first aspect of the present invention provides a semiconductor device, comprising electrodes formed on the surface of a first resin sealed package for sealing a semiconductor chip with a resin. The resin sealed package comprises a mounting area connected to electrodes of the semiconductor chip, an area to mount an object, and an area for connecting testing equipment.
According to the above structure, the step of selecting a HQC using an inexpensive testing socket or the like can be carried out without the fear of breaking the semiconductor chip. Stated more specifically, the semiconductor chip is incorporated in a resin sealed package and electrodes formed on the surface of the resin sealed package are each divided into a testing area and a mounting area to eliminate the electrode from being scratched by a screening test at the time of packaging. As the semiconductor chip is incorporated in a resin sealed package and handled in a test as an individual piece, the BT can be carried out on the resin sealed package in the same manner as in the prior art. That is, the screening step in the prior art, which needed to be carried out very carefully so as not to scratch the surface electrodes connected to the bonding wires, and to not break the semiconductor chip, can now be carried out easily at a low cost. Further, since the semiconductor chip is incorporated in a resin sealed package, it is hardly affected by the surrounding environment, such as water and stains, and its storage and preservation, which have been very difficult in the prior art, become easy.
The object to be mounted on the resin sealed package is a mounting substrate or a TCP (Tape Carrier Package) when a single resin sealed package incorporating a semiconductor chip is used. In the case of two or more resin sealed packages, each incorporating a semiconductor chip, that is, the MCP, electrodes formed on the surface of one resin sealed package are mounted to another resin sealed package, which in turn is mounted on a mounting substrate or TCP. The equipment used to test the package may be, for example, a testing socket, contact pin, prober or the like.
A second aspect of the present invention provides a semiconductor device comprising a first resin sealed package for sealing a semiconductor chip with a resin, and a second resin sealed package for sealing the first resin sealed package on a mounting substrate. Electrodes are formed on the surface of the first resin sealed package so as to comprise an area to be connected to an electrode of the semiconductor chip, a mounting area for an object, and a testing area for connecting testing equipment.
According to the above structure, there can be provided a HQC which has a mounting area and a testing area and incorporates a resin sealed package (first resin sealed package) in place of a semiconductor chip of the conventional art.
Japanese Patent Application Laid-open No. Heisei 11-40617 proposes a technology for providing electrodes for testing a semiconductor chip. The technology will be described hereinbelow with reference to FIG.
2
. As shown in
FIG. 2
, the technology disclosed by Japanese Patent Application Laid-open No. Heisei 11-40617 utilizes test pads
1014
which are formed on a TCP (Tape Carrier Package)
1010
for mounting a semiconductor chip. Connection pads are extended on the TCP
1010
and connected to the electrodes of the semiconductor chip. Numeral
1011
is a tape basement, numeral
1011
a
is an unit region, numeral
1012
is a wiring pattern, numeral
1012
b
is wiring extension pattern, numeral
1013
is a terminal for an external connection, numeral
1015
is a sprocket hole and numeral
1016
is a resist film.
However, according to this structure, a high-precision handler or the like must be used to handle the fragile semiconductor chip, as in th
NEC Electronics Corporation
Sughrue & Mion, PLLC
Thai Luan
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