Method for varying initial value in gray scale modification

Details Method for varying initial value in gray scale modification Method for varying initial value in gray scale modification

2000-09-19

2004-06-08

Razavi, Michael (Department: 2672)

Computer graphics processing and selective visual display system

Display driving control circuitry

Intensity or color driving control

C345S605000, C345S691000

Reexamination Certificate

active

06747669

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to an image processing technology and, more particularly, to a method for varying an initial value in a pseudo-gray scale modification.
DESCRIPTION OF THE RELATED ART
A liquid crystal display panel and a plasma display panel are examples of a thin video image producing apparatus. In the following description, term “display panel” is used for the thin video image producing apparatus. Pieces of video data information are usually supplied to the display panel through a digital signal. The gradation of image produced on the display panel is dependent on the bits of the digital video data signal. When a piece of video data information is represented by six bits, the panel display is able to produce 64 gray levels. On the other hand, if the digital video signal contains eight bits representing a piece of video data information, the gradation range is expanded to 256 gray levels. The gradation has been changed from 6-bit gradation to 8-bit gradation.
Digital chrominance signals are assumed to carry a piece of video data information representative of a full color image. The piece of video data information is broken down into three sub-pieces of video data information representative of a sub-image colored in red, a sub-image colored in green and a sub-image colored in green, and the chrominance signals are respectively assigned to the three sub-pieces of video data information. In the following description, “R”, “G” and “B” stand for red, green and blue, respectively. When the gradation is changed from 6 bits to 8 bits, each of the chrominance signals requires two additional bits, and an image data processing circuit is enlarged.
A display panel is assumed to have the resolution “SXGA”, i.e., 1280 lines ×1024 lines. In order to produce a full color image on the display panel from a piece of data information, the display panel requires two ports {(RA, GA, BA), (RB, GB, BB)}, and the piece of image data information is supplied through the two ports to a controller. The output signals of the controller are reduced in frequency, and arc supplied through four ports to a driver. The controller and the driver are in the form of semiconductor integrated circuit device, and are mounted on a circuit board. Various signal lines are printed on the circuit board, and the output signals are supplied from the controller through the signal lines to the driver. The number of signal lines is calculated as 8 bits ×3 colors ×4 ports, and is 96 lines. If each of the chrominance signals includes 6 bits representative of the sub-piece of video data information, only 72 signal lines propagate the output signals. Thus, the increase of gray levels results in the enlargement of the circuit board. Moreover, the driver circuit copes with the increase of the gray levels, and is also enlarged. This results in increase of the production cost.
As described hereinbefore, the enhancement of gradation results in the enlargement of the video data processing circuit. If the video data processing circuit for the 6-bit gradation is available for the video image represented by the 8-bit video signal, the production cost is restricted. For this reason, a pseudo-gray scale modification technique such as the dither technique or the frame rate controlling technique is employed in the video data processing circuit.
One of the pseudo-gray scale modification techniques is constructed on the basis of the error diffusion, and an example is disclosed in Japanese Patent Publication of Unexamined Application No. 9-90902. The Japanese Patent Publication of Unexamined Application teaches that the error diffusion is carried out in the direction of line and that the initial value is varied at every line and every frame. The prior art pseudo-gray scale modification is hereinbelow described in detail.
FIG. 1
shows a typical example of the error diffusion circuit. The prior art error diffusion circuit has two ports (not shown), and 8-bit video data signals RA, GA, BA and RB, GB, BB are sequentially input to the associated ports. Each of the 8-bit video data signals is separated into six high-order bits and two low-order bits. The six high-order bits are directly supplied to an input port “a” of an adder
107
, and the two low-order bits are supplied through an adder
106
to the other input port “b” of the adder
107
. The two low-order bits are supplied to an input port “c” of the adder
106
, and a carry bit is supplied from a carry port “CRY” of the adder
106
to the input port “b” of the adder
107
, and the adder
107
outputs 6-bit video data signals RA/GA/BA and RB/GB/BB.
An initial value generator
101
and a flip-flop circuit
103
are connected in parallel to two input ports “1”/“0” of a selector
102
. The initial value generator
101
supplies 2-bit signal representative of an initial value to the input port “1” of the selector
102
, and the flip-flop circuit
103
supplies the previous sum “c+d” to the input port “0” of the selector
102
. The selector
102
is responsive to a control signal
105
so as to selectively connect the input ports “1” and “0” to the output port “Y”. The output port “Y” of the selector
102
is connected to the other input port “d” of the adder
106
. The adder
106
adds the value at the input port “d” to the value at the input port “c”, and produces the sum “c+d” and the carry. The sum “c+d” is supplied from the output port “c+d” to an input port “D” of the flip-flop circuit
103
, and the carry is supplied from the carry port “CRY” to the input port “b” of the adder
107
. An internal clock signal
104
is supplied to the clock node “CK” of the flip-flop circuit
103
, and the flip-flop circuit
103
latches the sum “c+d” in response to the internal clock signal
104
.
When the first video data signal RA
1
, GA
1
, BA
1
, RB
1
, GB
1
or BB
1
of each frame is supplied through the port, the control signal
105
instructs the selector
102
to connect the initial value generator
101
to the input port “d” of the adder
106
. The initial value is transferred through the selector
102
to the input port “d” of the adder
106
. The initial value is added to the value represented by the two low-order bits of the first video data signal RA
1
/GA
1
/BA
1
/RB
1
/GB
1
/BB
1
. Then, the sum “c+d” is produced. The sum “c+d” is representative of an error. If the carry takes place, the carry bit is supplied from the adder
106
to the input port “b” of the adder
107
, and is added to the six high-order bits.
The control signal
105
instructs the selector
102
to change the input port from “1” to “0”. When the next internal clock signal is changed to the active level, the sum “c+d” is latched by the flip-flop circuit
103
. The sum “c+d” is transferred through the selector
102
to the input port “d”, and is added to the two low-order bits of the second video data signal of the same frame. The control signal
105
keeps the signal propagation path from the input port “0” to the output port “Y” in the selector
102
until the last video data signal.
When the first video data signal of the next frame is supplied to the port, the control signal
105
instructs the selector
102
to connect the input port “1” to the output port “Y”. The initial value generator
101
supplies an initial value through the selector
102
to the input port “d” of the adder
106
. However, the initial value is not fixed. When the line or the frame is changed, the initial value generator
101
changes the initial value.
In the prior art error diffusion circuit disclosed in Japanese Patent Publication of Unexamined Application No. 9-90902, three low-order bits are added to the previous sum, i.e., the error, and the error is circulated. The initial value generator changes the initial value as shown in FIG.
2
. Eight lines form a line group, and the initial value is changed in every line group of each odd frame as “7”, “1”, “2”, “4”, “3”, “5”, “6” and “0”. On the other hand, the initial value generator changes the initi

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