Bus interface circuit for an intelligent low power serial bus

Details Bus interface circuit for an intelligent low power serial bus Bus interface circuit for an intelligent low power serial bus

1995-08-18

1998-07-28

Harvey, Jack B.

39575002, 395285, 395309, G06F 132

Patent

active

057872988

ABSTRACT:
A low power, single master, variable clock rate, daisy-chainable, serial bus connects a bus dispatch (master) to a chain of one or more daisy-chained peripheral devices (slaves). The bus has a bidirectional serial data line, a bidirectional clock line, unidirectional interrupt line, power and ground lines. Each peripheral device includes a first bidirectional signal line, a second bidirectional signal line coupled to the bus clock and data lines, respectively, and an interface circuit coupled to the first and second bidirectional signal lines. The interface circuit includes a first buffer circuit coupled to the first and second bidirectional signal lines, and a second buffer circuit coupled to the first buffer circuit. A control circuit in the interface circuit couples the first and second buffer circuits where in a first mode of operation, the control circuit passes signals on the first and second bidirectional signal lines through the first and second buffer circuits, and in a second mode of operation, the control circuit passes signals on the first and second bidirectional signal lines through the first buffer circuit and configures the second buffer circuit to terminate the first bidirectional signal line. Thus bus power supply line is coupled to the interface circuit and a voltage on the power supply line is used to power the first and second buffer circuits and the control circuit. The bus interrupt line is coupled to the control circuit of the interface circuit. The interface circuit is also coupled to signal lines of the peripheral device.

REFERENCES:
patent: 5317693 (1994-05-01), Cuenod et al.
patent: 5404460 (1995-04-01), Thomsen et al.
patent: 5542035 (1996-07-01), Kikinis et al.

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