Data processing: structural design – modeling – simulation – and em – Structural design
Reexamination Certificate
2002-07-02
2004-10-05
Pert, Evan (Department: 2829)
Data processing: structural design, modeling, simulation, and em
Structural design
C029S593000
Reexamination Certificate
active
06801880
ABSTRACT:
BACKGROUND
The disclosures herein relate generally to information handling systems and more particularly to a system and method for minimizing a loading effect of a via by tuning a cutout ratio.
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
Information handling systems are often manufactured using a circuit board that mounts and couples numerous components. The circuit board typically includes a plurality of power and signal layers that are used to convey power and signals between the components of the system. The power and signal layers are sandwiched between insulation layers to prevent current transfer between the layers. The layers include signal paths known as traces. To route a signal between layers of the board, a via connects traces between the different layers. Unfortunately, the use of vias present loading effects on signals that may cause impedance and other electrical parameter discontinuities along the traces. As a result, signal integrity may be affected, particularly at high signal speeds.
It would be desirable to be able to minimize the loading effects of a via on a circuit board. Accordingly, what is needed is a system and method for minimizing a loading effect of a via by tuning a cutout ratio.
SUMMARY
One embodiment, accordingly, provides an information handling system that includes a circuit board for mounting and coupling components of the information handling system. The circuit board includes a trace, a via coupled to the trace, and a cutout region surrounding the via and having a first diameter selected to minimize a loading effect of a via on a signal conveyed on the trace.
A principal advantage of this embodiment is that various shortcomings of previous techniques are overcome. For example, a loading effect of a via on a circuit board may be minimized.
REFERENCES:
patent: 3859711 (1975-01-01), McKiddy
patent: 4285780 (1981-08-01), Schachter
patent: 5450290 (1995-09-01), Boyko et al.
patent: 5459287 (1995-10-01), Swamy
patent: 5477082 (1995-12-01), Buckley, III et al.
patent: 5530288 (1996-06-01), Stone
patent: 5558928 (1996-09-01), Distefano et al.
patent: 5585162 (1996-12-01), Schueller
patent: 5706178 (1998-01-01), Barrow
patent: 5784262 (1998-07-01), Sherman
patent: 5796589 (1998-08-01), Barrow
patent: 5812379 (1998-09-01), Barrow
patent: 5841074 (1998-11-01), Egan et al.
patent: 5875102 (1999-02-01), Barrow
patent: 5972734 (1999-10-01), Carichner et al.
patent: 6050832 (2000-04-01), Lee et al.
patent: 6137709 (2000-10-01), Boaz et al.
patent: 6144576 (2000-11-01), Leddige et al.
patent: 6201194 (2001-03-01), Lauffer et al.
patent: 6233820 (2001-05-01), Hummelink
patent: 6362973 (2002-03-01), Leddige et al.
patent: 6366466 (2002-04-01), Leddige et al.
patent: 6373139 (2002-04-01), Clark
patent: 6395378 (2002-05-01), Bergstedt et al.
patent: 6486414 (2002-11-01), Kobayashi et al.
patent: 40294693 (1990-04-01), None
patent: 06037416 (1994-02-01), None
Teshome Abeye
Zhang Lan
Dell Products L.P.
Haynes and Boone LLP
Pert Evan
LandOfFree
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