Radiant energy – Photocells; circuits and apparatus – Photocell controlled circuit
Reexamination Certificate
2002-05-17
2004-08-10
Porta, David (Department: 2878)
Radiant energy
Photocells; circuits and apparatus
Photocell controlled circuit
C348S311000, C348S314000
Reexamination Certificate
active
06774350
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a solid state imaging device having a plurality of light receiving pixels arranged in a matrix-like manner and a method for driving such solid state imaging device.
In an imaging device, such as a digital camera, a preview of a captured image is shown as a dynamic image. The resolution of a preview does not have to be as high as a still image. Thus, image signals, which are output from a solid state imaging device, are thinned out to generate the dynamic image.
FIG. 1
is a schematic circuit block diagram of a prior art imaging device
50
.
FIG. 2
is a timing chart illustrating the horizontal transfer and output operation of the imaging device
50
.
FIG. 1
shows a solid state imaging device
1
having a matrix formed by six rows and eight columns. The solid state imaging device
1
has a light receiving portion for generating information charges. An output section
1
d
of the solid state imaging device
1
synthesizes a predetermined amount of the information charges to thin out the image signals.
The solid state imaging device
1
is, for example, a frame transfer type device. The solid state imaging device
1
includes a light receiving portion
1
i
for receiving a captured image and generating information charges, a storage portion
1
s
for temporarily storing the generated information charges, a horizontal shift register
1
h
for transferring the information charges in the row (horizontal) direction, and the output section
1
d
for converting the information charges to a voltage having a value that is in accordance with the charge amount of the information charges.
The drive circuit
2
includes a frame transfer clock generation circuit
2
f
, a vertical transfer clock generation circuit
2
v
, a horizontal clock generation circuit
2
h
, a reset clock generation circuit
2
r
, a sampling clock generation circuit
2
s
, and a substrate clock generation circuit
2
b.
In response to a frame transfer timing signal FT, the frame transfer clock generation circuit
2
f
generates, for example, a frame transfer clock &PHgr;
f
having four phases and provides the frame transfer clock &PHgr;
f
to the light receiving portion
1
i
. Information charges for a single screen image, which are accumulated in light receiving pixels of the light receiving portion
1
i
, are transferred to the storage portion
1
s
in accordance with the frame transfer clock &PHgr;
f
and in synchronism with a vertical scanning period.
In response to a vertical synchronizing signal VT and a horizontal synchronizing signal HT, the vertical transfer clock generation circuit
2
v
generates, for example, a vertical transfer clock &PHgr;v having four phase and provides the vertical transfer clock &PHgr;v to the storage portion
1
s
. The information charges received from the light receiving portion
1
i
are temporarily accumulated in the storage portion
1
s
in accordance with the vertical transfer clock &PHgr;v and in synchronism with a frame transfer timing. The accumulated information charges are provided to the horizontal shift register
1
h
in units of rows for each horizontal scanning period
1
H.
In response to the horizontal synchronizing signal HT, the horizontal transfer clock generation circuit
2
h
generates, for example, a transfer clock &PHgr;h having two phases and provides the frame transfer clock &PHgr;h to the horizontal shift register
1
h
. The information charges corresponding to a single row, which is received in each bit register of the horizontal shift register
1
h
, is provided to the output section id sequentially in units of single pixels.
The reset clock generation circuit
2
r
generates a reset clock &PHgr;r in synchronism with the horizontal transfer clock generation circuit
2
h
and provides the reset clock &PHgr;r to the output section
1
d
. The information charges transferred from the horizontal shift register
1
h
in units of single pixels are converted to a voltage having a value that is in accordance with the charge amount in response to the reset clock &PHgr;r and sequentially output.
In the same manner as the reset clock generation circuit
2
r
, the sampling clock generation circuit
2
s
generates the sampling clock &PHgr;s in synchronism with the operation of the horizontal transfer clock generation circuit
2
h
and provides the sampling clock &PHgr;s to the sample hold circuit
4
. In accordance with the sampling clock &PHgr;s and in synchronism with the horizontal scanning period, among the reset level and the signal level, which are repeated in an image signal Y
0
(
t
), only the signal level is extracted to generate an image signal Y
1
(
t
) having consecutive signal levels.
In response to a drain timing signal BT, the substrate clock generation circuit
2
b
generates a substrate clock &PHgr;b that disposes of information charges accumulated in the light receiving portion
1
i
and provides the substrate clock &PHgr;b to a substrate side of the solid state imaging device
1
.
The timing control circuit operates in accordance with a reference clock CK having a constant cycle. The timing control circuit
3
generates the vertical synchronizing signal VT and the horizontal synchronizing signal HT, which determine the vertical and horizontal scanning timing of the solid state imaging device
1
, and generates a frame transfer timing signal FT at a cycle coinciding with the vertical synchronizing signal VT. The timing control circuit
3
generates the drain timing signal BT in accordance with integral data that represents the integral value of a single screen image provided from a digital signal processing circuit (not shown) or the integral value of an arbitrary section.
The drain timing signal BT is provided to the drive circuit
2
together with the vertical synchronizing signal VT, the horizontal synchronizing signal HT, and the frame transfer timing signal FT. The drain timing signal BT delays the drain timing when the integral data exceeds a value that is adequate for shortening the storage time of the information charges. On the other hand, the drain timing signal BT advances the drain timing when the integral value becomes smaller than the adequate value to lengthen the storage time. To optimize the exposure state of the solid state imaging device
1
, feedback control is performed in accordance with the drain timing signal BT.
A dividing circuit
5
includes a first divider
5
a
for dividing the sampling clock &PHgr;s and a second divider
5
b
for dividing the reset clock &PHgr;r. The dividing circuit
5
divides the reset clock &PHgr;r and the sampling clock &PHgr;s when necessary. The output section
1
d
is operated intermittently in accordance with the divided reset clock &PHgr;r and the divided sampling clock &PHgr;s to mix information charges.
For example, when the cycle of the reset clock &PHgr;r, the cycle of which is the same as that of the horizontal transfer clock &PHgr;h, is divided by ½, a reset clock &PHgr;r′ having a cycle that is two times longer is generated. The reset clock &PHgr;r′ resets the information charges whenever information charges for two pixels are accumulated in the output section
1
d
. This synthesizes the information charges for two pixels, which are arranged adjacent to each other in the horizontal direction, and thins out the information charges.
In the prior art imaging device
50
, a color filter is attached to the light receiving portion
1
i
when performing color imaging. The color filter includes a plurality of different segments corresponding to the three primary colors and their auxiliary colors. The segments are arranged in a two dimensional manner and correspond in a regular manner with each light receiving pixel. In the color imaging solid state imaging device
1
that associates certain color components with each light receiving pixel, the color components of the light receiving pixels adjacent to each other in the horizontal direction are different. Thus, the information charges of pixels in the horizontal direct
Lee Patrick J.
Porta David
Sanyo Electric Co,. Ltd.
Sheridan Ross PC
LandOfFree
Solid state imaging device and method for driving solid... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Solid state imaging device and method for driving solid..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Solid state imaging device and method for driving solid... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3313761