Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
2000-12-15
2004-02-10
Tugbang, A. Dexter (Department: 3729)
Metal working
Method of mechanical manufacture
Electrical device making
C029S620000, C029S852000, C324S760020
Reexamination Certificate
active
06687978
ABSTRACT:
TECHNICAL FIELD
This invention relates to methods of testing integrated circuitry, to methods of forming tester substrates, and to circuitry testing methods.
BACKGROUND OF THE INVENTION
Integrated circuitry fabricated in the semiconductor industry is tested at various phases for operability. Such occurs both before and after singulation of individual die relative to a semiconductor wafer bearing a plurality of such die. The individual die have a plurality of exposed conductors, such as flat bond pads, which are wired in electrical connection with the integrated circuitry of the die. These bond pads ultimately might be connected with other circuitry of other substrates by metal wires which are bonded thereto. Alternately by way of example only, the exposed conductors of the individual die might comprise other projections, such as conductive balls/bumps conductively bonded with the bond pads.
During testing, the exposed conductors are engaged with a suitable tester substrate, such as a probing device or some other suitable testing device. Current is then caused to flow between the testing apparatus and the circuitry through the exposed conductors thereof for one or both of operability testing or stressing of the circuitry on the wafer. For example, low temperature testing might be conducted at room temperature up to 80° C. Further, burn-in operability cycling of the circuitry on the chip has also been conducted at temperatures at or below 125° C. An intent of the elevated temperature testing might be to verify operation of the circuitry in such environments if it is intended to operate at such elevated temperatures. Further, burn in testing is conducted in an attempt to stress the circuitry and simulate its operational life at normal operating temperatures by subjecting the wafer to the elevated temperature operability testing.
One problem associated with the prior art burn-in and testing is described with respect to FIG.
1
. There illustrated is a substrate
10
comprising integrated circuitry to be tested. Substrate
10
includes a monolithic chip
12
having integrated circuitry fabricated therein. Chip
12
is adhesively bonded to a printed circuit board-like substrate
14
also having conductive traces formed thereon. Substrate
14
comprises opposing surfaces
15
and
17
. Chip
12
is bonded to surface
15
, and includes a plurality of wire bonds
18
conductively bonded between bond pads or other connections of chip
12
and conductive traces formed on surface
15
of substrate
14
. Wires
18
, chip
12
and surface
15
of substrate
14
are encapsulated in a suitable cured encapsulant
19
to hermetically seal and protect the chip and bond wires. Side
17
of substrate
14
includes a plurality of conductive bond sites
20
formed in electrical connection with certain sites to which bond wires
18
electrically connect on opposing side
15
. A plurality of electrically conductive ball bumps
21
,
22
and
23
are conductively bonded with sites
20
. Accordingly, such constitutes but one example of a plurality of exposed conductors in electrical connection with integrated circuitry, here in the form of chip
12
and substrate
14
, of which burn-in and/or operability testing is to be conducted.
Certain prior art testing utilized probe pins or receptacles or jackets which contacted each of balls
21
,
22
and
23
for providing the electrical connection for tests. However, the ever-increasing goal for more miniaturization in circuitry fabrication reached a point where pitch of adjacent balls fell below 1 millimeter. At around 0.5 millimeter and below, it became very difficult to both fabricate and probe substrates such as device
10
for test and burn-in cycling. One solution to this problem was to fabricate at least a portion of the testing substrate of a semiconductor wafer processed utilized photolithographic processing. Such enables precise patterning of testing locations on a testing substrate which can be closely fabricated adjacent one another to register with the exposed conductors of other substrates to be tested. One such substrate is illustrated as component
25
in FIG.
1
. Substrate
25
includes a plurality of conductive receptacles
28
lined with a suitable conductor
29
, and is shown diagrammatically. The reader is directed to consider possible construction disclosed in our U.S. Pat. No. 5,592,736, which is herein incorporated by reference.
It is desirable to fabricate each of the exposed conductors, such as conductive balls
21
,
22
and
23
, to be of substantially the same size. This would more readily assure desired contact of all of the respective balls with their registered conductive receptacles. However as processing dimensions continue to get smaller, tolerance for minor variation in exposed conductor size decreases.
FIG. 1
shows an exaggerated view of each of the exposed conductors
21
,
22
and
23
being of different size. Conductor
23
is shown to be within example tolerance limits for being received suitably within its registered receptacle
28
for burn-in and/or testing. However, exposed conductors
21
and
22
are shown to be too large and too small, respectively, outside of desired tolerance limits. Further, the oversize nature of exposed conductor
21
, while making electrical connection with its registered receptacle
28
, unfortunately precludes any desired contact in the illustrated example with exposed conductors
22
and
23
. Accordingly, suitable test and/or burn-in of the integrated circuitry of substrate
10
will not occur.
SUMMARY OF THE INVENTION
The invention comprises in preferred embodiments methods of testing integrated circuitry, methods of forming tester substrates, and circuitry testing substrates. A method of testing integrated circuitry includes providing a substrate comprising integrated circuitry to be tested. The circuitry substrate to be tested has a plurality of exposed conductors in electrical connection with the integrated circuitry. In one implementation, at least some of the exposed conductors of the circuitry substrate are heated to a temperature greater than 125° C. and within at least 50% in degrees centigrade of and below the melting temperature of the exposed conductors of the circuitry substrate. In one implementation, such are heated to a temperature below their melting temperature yet effective to soften said at least some of the exposed conductors to a point enabling their deformation upon application of less than or equal to 30 grams of force per exposed conductor. The circuitry substrate is engaged with a tester substrate. The tester substrate has a plurality of exposed conductors at least some of which are positioned to align with exposed conductors of the circuitry substrate. The engaging occurs while the at least some conductors of the circuitry substrate are heated to temperature and comprises contacting at least some of the exposed conductors of the tester substrate with conductors of the circuitry substrate. The integrated circuitry is tested through said conductors of the circuitry substrate and the tester substrate.
In one aspect, a method of forming a tester substrate for testing circuitry having a plurality of exposed conductors includes forming a plurality of conductive receptacles at least partially received into a surface of a substrate. The receptacles are sized to receive one of the plurality of exposed conductors of circuitry being tested. A resistive receptacle heating element supported by the substrate is formed proximate at least a portion of at least some of the conductive receptacles.
In one aspect, a circuitry testing substrate comprises an outer substrate surface having a plurality of conductive receptacles formed into said surface. Resistive receptacle heating elements are supported by the substrate and are received proximate the conductive receptacles, and are spaced from conductive portions of the conductive receptacles.
Other aspects follow are contemplated.
REFERENCES:
patent: 3596228 (1971-07-01), Reed, Jr. et al.
patent: 4975079 (1990-12-01), Beaman
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Tugbang A. Dexter
Wells St. John P.S.
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