Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2001-07-05
2004-12-07
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S499000, C257S510000, C257S513000, C257S517000
Reexamination Certificate
active
06828651
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of electronic circuits, and, more particularly, to integrated structures formed on semiconductor chips.
BACKGROUND OF THE INVENTION
Integrated structures are often formed in semiconductor chips and include a substrate which has a high concentration of impurities, i.e., with doping of the P+ type (or N+ type). Further, an epitaxial layer may be included which has a conductivity of the same type as that of the substrate, but a low concentration of impurities, i.e., with doping of the P− type (or N− type). These structures are commonly called “P+P−” (or N+N−) structures. The epitaxial layer also has suitably doped regions formed therein, inside of which electronic components or circuit groups are formed.
One known technology for power applications is bipolar-CMOS-DMOS (BCD) technology. BCD technology allows for the integration of several output power devices, which is particularly advantageous when it is necessary to construct half-bridge or whole-bridge circuits both of the single-phase and three-phase type, or when a large number of parallel outputs are required. The need to have several isolated outputs in certain applications results in the use of a substrate having a polarity different from that of a collector of a bipolar transistor, or from that of a drain of a metal oxide semiconductor (MOS) transistor, which are integrated in the epitaxial layer.
Consequently, in BCD technology, the integrated components include terminals which, for isolation, are located on the surface of the semiconductor chip. In particular, in the context of BCD technology and for power applications where relatively low supply voltages are required (i.e., typically, but not exclusively, ranging between 30 V and 60 V), P+P− structures are typically used. In such cases, the P+P− structures have a relatively small epitaxial layer thickness of between 5 &mgr;m and 7 &mgr;m, for example.
In general, the electronic components or the circuit groups formed in a structure integrated in a semiconductor chip must be electrically isolated from each other. One widely used isolating technique includes creating isolating regions inside the semiconductor chip which have a conductivity of the type opposite to that of the semiconductor material. These isolating regions are biased with respect to the semiconductor material so that the PN junctions which they form with the material are reverse-biased. The reverse-biasing of these regions, which include various components or circuit groups, ensures that they are isolated under normal operating conditions.
Undesired current may flow in integrated structures including two or more isolating regions or other regions with a conductivity of the type opposite to that of the semiconductor material inside which they are formed. The undesired current may cause abnormal operation of the integrated structure to occur. These currents are caused by transient direct biasing of the junctions which, during normal operation, are reverse-biased.
For example, in the case of power applications of the integrated structure, this direct biasing may occur upon switching of polarity in inductive loads, such as inductances or motors, or in capacitive loads, such as capacitors, batteries and accumulators. Moreover, the current generated by injection of charges from a region directly biased with respect to the semiconductor material in which it is formed may reach a further region similar to the directly biased region, but that is reverse-biased.
In this situation a lateral parasitic bipolar transistor is formed. The two homologous regions forming the emitter and the collector and the intermediate semiconductor material form the base thereof. It is noted here that the formation of parasitic transistors is a particularly serious problem for technologies such as BCD technology and complementary MOS (CMOS) technology, where several components each with an output designed to assume a different potential are formed on a single integrated circuit. Generally, this phenomena is also known by the term “latch-up”.
Various techniques aimed at reducing the effects of formation of these lateral parasitic transistors are known. According to a first technique, the two homologous regions are suitably spaced to reduce the gain of the parasitic transistor. This technique involves a considerable reduction in the area of the integrated structure which can be used for other circuit components.
According to another technique, the portion of semiconductor material located between the two homologous regions, i.e., the base of the parasitic transistor, is more heavily doped to reduce the gain of this transistor. This technique has the disadvantage that, in power applications, a strong electrical field may be created. To reduce the effect of this electrical field, it is necessary to form a suitable termination structure for the homologous regions, which results in considerable waste of the chip area.
According to a further technique, an additional region having a conductivity opposite to that of the epitaxial layer is formed in the epitaxial layer and between the homologous regions. This additional region allows division of the parasitic component between the homologous regions in two lateral parasitic transistors having a common base, formed by the substrate.
This intermediate region is electrically connected to the epitaxial layer by a superficial metal contact strip. This reduces locally the substrate potential, preventing bias conditions and current injection from occurring. This technique requires a suitable termination structure, which also results in a considerable amount of space being used. Moreover, in the case of P+P− structures, it does not guarantee significant results since these structures, owing to the fact that the P+ substrate has a high conductivity and a low value resistance to ground. This makes it difficult to achieve the desired reduction in the substrate potential.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device and related methods which overcome the above mentioned drawbacks of the prior art and that are effective and relatively easy to apply.
This and other objects, features, and advantages of the present invention are provided by an integrated structure formed on a semiconductor chip and including a substrate having a first type of conductivity, and an epitaxial layer grown on the substrate and also having the first conductivity type. The epitaxial layer may have a conductivity which is less than the conductivity of the substrate. Further, first and a second regions may be included in the epitaxial layer having a conductivity opposite to that of the epitaxial layer. The first and second regions may extend from a surface of the epitaxial layer opposite the substrate into the epitaxial layer to form first and second junctions therewith.
The integrated structure may also include a means for reducing an injection of current through the epitaxial layer from the first to the second region when the first junction is directly biased. The means may include an isolating element located between the first and second region that extends from the surface of the epitaxial layer at least as far as the substrate.
A method for producing an integrated structure according to the invention is also provided.
REFERENCES:
patent: 4416050 (1983-11-01), Sarace
patent: 4631803 (1986-12-01), Hunter et al.
patent: 5034785 (1991-07-01), Blanchard
patent: 5476809 (1995-12-01), Kobayashi
patent: 5597742 (1997-01-01), Zambrano
patent: 5736445 (1998-04-01), Pfirsch
patent: 5757081 (1998-05-01), Chang et al.
patent: 5990537 (1999-11-01), Endo et al.
patent: 5998822 (1999-12-01), Wada
patent: 6175277 (2001-01-01), Mavencamp
patent: 6184565 (2001-02-01), Beasom
patent: 6184566 (2001-02-01), Gardner et al.
patent: 6239465 (2001-05-01), Nakagawa
patent: 6452230 (2002-09-01), Boden, Jr.
patent: 0292972 (1988-11-01), None
patent: 0429131 (199
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Flynn Nathan J.
Jorgenson Lisa K.
Mondt Johannes
STMicroelectronics S.r.l.
LandOfFree
Integrated structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3313373