Multichip package

Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices

Reexamination Certificate

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Details

C361S689000, C361S719000, C257S706000, C257S712000, C165S080300

Reexamination Certificate

active

06833993

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to a chip package, and more particularly to a multichip package.
2. Description of the Related Art
As electronic devices have become more smaller and thinner, the packages for protecting IC chips and interconnecting the IC chips to exterior circuit have the same trend, too.
With ever increasing demands for miniaturization and higher operating speeds, multichip packages are increasingly attractive in a variety of electronics. Multichip packages that contain more than one chip can help minimize the system operational speed restrictions by combining two or more chips, for example, the processor, memory, and associated logic, into a single package. In addition, multichip packages decrease the interconnection length between IC chips thereby reducing signal delays and access times.
The most common multichip packages are the side-by-side multichip packages and stacked multichip packages. In the side-by-side multichip package, two or more IC chips are mounted next to each other (or side by side each other) on the principal mounting surface of a common substrate. Interconnections among the chips and conductive traces on the substrate are commonly made via wire bonding. In the stacked multichip package, two or more IC chips are stacked on each other in order on a substrate and respectively wire bonded to the substrate.
However, when the multichip package comprises an IC chip with high density and high frequency digital circuitry, the layout of the corresponding conductive traces on the substrate and I/O pads must be widened. If the side-by side multichip package is used in such case, the distance between the IC chip and the other chips will be significantly increased such that the package efficiency will be reduced. In another aspect, each IC chip, especially IC chips with high density and high frequency digital circuitry, will generate heat during operation. If the IC chips are stacked, the heat generated by the middle or the bottom layer IC chips can hardly be dissipated; therefore, the IC chip will be easily damaged, which adversely affects the quality of product.
Therefore, a multichip package is needed to overcome or at least solve the aforementioned problems of the prior arts.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a multichip package which comprises at least one first chip with high density and high frequency digital circuitry and at least one auxiliary second chip, wherein the first and the second chip are respectively disposed on the opposing upper and lower surfaces of the substrate, thereby decreasing the interconnection length between the chips and improving the electrical performance of the package.
It is another object of the present invention to provide a multichip package using flip-chip technology to eliminate package body thereof such that the first chip is exposed to the environment thereby increasing the thermal performance of the package.
It is still another object of the present invention to provide a multichip package with a heat spreader disposed in the upper surface of the substrate thereof and covering the area corresponding to the first chip thereby dissipating heat generated by the first chip efficiently and increasing the thermal performance of the package.
The multichip package in accordance with the present invention mainly comprises a substrate, a first chip disposed on the lower surface of the substrate, at least one second chip and a heat spreader disposed on the upper surface of the substrate, wherein the first chip is disposed on the substrate by flip-chip bonding and the heat spreader is attached to the substrate via a thermal conductive epoxy.
The present invention is characterized in that the heat spreader on the upper surface of the substrate covers the projective area corresponding to the first chip and preferably covers the entire projective area of the first chip thereby efficiently dissipating the heat generated by the first chip under normal operation. It is preferred that the heat spreader is made of good thermal-conductive metal like copper or aluminum. The heat spreader covers substantially the entire upper surface of the substrate except the area occupied by the second chip thereby efficiently using the spare space. Too much thickness of the heat spreader is not necessary, it is preferred that the top surface of the head spread is not higher than the top surface of the second chip, and it is more preferred that the top surface of the head spread and the top surface of the second chip are substantially coplanar.
Generally, the substrate is made of poor thermal conductive material; therefore, at least one thermal via which extends through the substrate is provided for conducting the heat generated by the first chip to the heat spreader, and at least one thermal trace which extends on the upper surface of the substrate is provided for conducting the heat generated by the second chip to the heat spreader.
Furthermore, the second chip can be disposed on the upper surface of the substrate by flip-chip bonding or conventional wire-bonding method and encapsulated by a package body.
Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5477082 (1995-12-01), Buckley et al.
patent: 5909056 (1999-06-01), Mertol
patent: 6118177 (2000-09-01), Lischner et al.
patent: 6201301 (2001-03-01), Hoang
patent: 6376917 (2002-04-01), Takeshita et al.
patent: 6462421 (2002-10-01), Hsu et al.
patent: 6472762 (2002-10-01), Kutlu
patent: 6507115 (2003-01-01), Hofstee et al.
patent: 6545351 (2003-04-01), Jamieson et al.
patent: 6765152 (2004-07-01), Giri et al.
patent: 2004/0150098 (2004-08-01), Lee

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