Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2003-10-09
2004-08-17
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
Reexamination Certificate
active
06777991
ABSTRACT:
BACKGROUND
1. Field
This patent disclosure relates to phase-locked loops, and more particularly to a method and apparatus for phase-locked looping capable of stably operating with reduced adverse effects including jitters.
2. Discussion
In recent years, designers have sought to reduce the electrical power needs of electric equipment. Accordingly, the power applied to a PLL (phase-locked loop) circuit should be decreased as well.
FIG. 1
shows an exemplary circuit of a known VCO (voltage-controlled oscillator)
100
having a power source Vdd. In
FIG. 1
, the VCO
100
includes a ring oscillator
101
, PMOS (P-channel metal oxide semiconductor) transistors P
1
-Pm, and NMOS (N-channel metal oxide semiconductor) transistors N
1
-Nm. The suffixes m of the PMOS and NMOS transistors Pm and Nm are an odd integers greater than 1. Further the VCO
100
includes a voltage-to-current conversion circuit
105
, a first current mirror circuit
106
, a second current mirror circuit
107
, a third current mirror circuit
108
, an NMOS (N-channel metal oxide semiconductor) transistor
109
, and a constant current source
110
.
The ring oscillator
101
includes inverter circuits IV
1
-IVm which form a delay circuit, wherein a suffix m is an odd integer greater than 1. The inverter circuits IV
1
-IVm are connected in a ring form. Each of the inverter circuits IV
1
-IVm of the ring oscillator
101
is composed of a pair of PMOS (P-channel metal oxide semiconductor) and NMOS (N-channel metal oxide semiconductor) transistors connected in series. The PMOS transistors P
1
-Pm are correspondingly connected to the inverter circuits IV
1
-IVm, respectively, and control a current flowing to a positive side power source terminal of the inverter circuits IV
1
-IVm from a direct current power source (not shown). The NMOS transistors N
1
-Nm are correspondingly connected to the inverter circuit IV
1
-IVm, respectively, and control a current flowing to a common ground from a negative side power source terminal of the inverter circuits IV
1
-IVm.
The voltage-to-current conversion circuit
105
includes an operational amplifier
102
, an NMOS (N-channel metal oxide semiconductor) transistor
103
, and a resistor
104
. The operational amplifier
102
is configured to have a negative feedback, and outputs the input voltage VCOIN to a gate terminal of the NMOS transistor
103
. Such operational amplifier
102
operates such that the voltage at the junction of the NMOS transistor
103
and the resistor
104
is substantially equal to the input voltage VCOIN. The current converted by the voltage-to-current conversion circuit
105
flows through the first, second, and third current mirror circuits
106
,
107
, and
108
and through the NMOS transistor
109
.
The NMOS transistor
109
forms a current mirror circuit with each of the NMOS transistors N
1
-Nm and therefore, a current in accordance with the current output from the third current mirror circuit
108
flows through each of the NMOS transistors N
1
-Nm. The PMOS transistor
115
of the third current mirror circuit
108
forms a current mirror circuit with each of the PMOS transistors P
1
-Pm, and therefore each of the PMOS transistors P
1
-Pm supplies a current to a positive side power source terminal of corresponding one of the inverter circuits IV
1
-IVm in accordance with the current output from the second current mirror circuit
107
.
In this way, a current flowing through each of the inverter circuits IV
1
-IVm can be controlled. That is, a delay time by each of the inverter circuits IV
1
-IVm can be controlled with using the input voltage VCOIN. Thereby, the VCO
100
can change the frequency of a signal SOUT output from the ring oscillator
101
with the input voltage VCOIN. In this type of PLL circuit, the oscillating frequency of the ring oscillator
101
is determined by the performances of the voltage-to-current conversion circuit
105
and the PMOS transistor
115
. In particular, a minimum oscillating frequency of the ring oscillator
101
is determined by a resistance value of the resistor
104
provided to the voltage-to-current conversion circuit
105
.
However, with the structure of the VCO
100
, the frequency of the signal SOUT output from the ring oscillator
101
is not always linear, as seen in FIG.
2
. More specifically, when the input voltage VCOIN is close to the power source voltage Vdd, the frequency of the signal SOUT linearly changes to an extent of a value obtained by subtracting a threshold voltage of the PMOS transistor
111
from the power source voltage Vdd.
That is, in a PLL circuit including the VCO
100
having a frequency characteristic shown in
FIG. 2
, the output frequency of the VCO
100
is linear relative to the input voltage VCOIN only in a narrow voltage range.
Therefore, it is needed to increase a gain of the VCO
100
. However, if the gain of the VCO is increased, a variation of the output frequency per input voltage becomes greater and consequently the PLL circuit will have a greater jitter. As a result, the PLL decreases its performance.
In
FIG. 2
, a line A
1
represents the frequency of the signal SOUT linearly increasing from a value greater than 0 as the input voltage VCOIN increases when a constant current source
110
is provided to the VCO
100
, as shown in
FIG. 1. A
line A
2
represents the frequency of the signal SOUT which linearly increases from 0, i.e., the ground level, when the constant current source
110
is not provided the VCO
100
.
Generally, an area requiring a relatively high voltage remains in an input and output portion associated with an external component even in a process having a decreased source voltage. In such an area, a transistor having a relatively low performance but suitable for a high voltage use is applied. Under this circumstance, one method for preventing a PLL circuit from the degradation of its performance with an increasing jitter is to maintain a voltage of the whole PLL circuit at a high level by using a transistor for a high voltage use. In this method, however, a level shifter is needed between the PLL circuit and an internal logic circuit to be connected to the PLL circuit and therefore the PLL circuit will degrade in a duty cycle and a jitter.
SUMMARY
This patent specification describes a novel phase-locked loop apparatus. In one example, a novel phase-locked loop apparatus includes a comparator, a filter, and a voltage-controlled oscillator. The comparator is configured to compare phases of a reference clock signal and an output signal of the apparatus and to output a voltage in accordance with a difference in phase as a comparison result. The filter is configured to integrate the voltage output from the comparator. The voltage-controlled oscillator is configured to control a frequency of an output signal in accordance with the voltage output from the filter. This voltage-controlled oscillator includes a ring oscillator, a plurality of first transistors, a plurality of second transistors, a voltage-to-current converter, a first current mirror circuit, a second current mirror circuit, and a third current mirror circuit. The ring oscillator is configured to include a delay circuit including a plurality of inverters connected in a ring form. The plurality of first transistors correspond to the plurality of inverters of the ring oscillator on a one-to-one basis and are configured to control a current supplied by a first power source voltage to a positive side power source terminal of each of the plurality of inverters. The plurality of second transistors correspond to the plurality of inverters of the ring oscillator on a one-to-one basis and are configured to control a current output from a negative side power source terminal of each of the plurality of inverters. The voltage-to-current converter is configured to convert the voltage output from the filter into a current. The first current mirror circuit is configured to output a current in accordance with the current output from the voltage-to-current converter. The second current mirror circuit is confi
Cooper & Dunham LLP
Zweizig Jeffrey
LandOfFree
Method and apparatus for stable phase-locked looping does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for stable phase-locked looping, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for stable phase-locked looping will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3310825