Solid-state imaging apparatus

Details Solid-state imaging apparatus Solid-state imaging apparatus

2000-02-25

2004-11-23

Christensen, Andrew (Department: 2615)

Television

Camera, system and detail

Optics

C348S362000, C348S312000, C348S296000

Reexamination Certificate

active

06822689

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a solid-state imaging apparatus having an exposure control function.
2. Description of the Related Art
FIG. 1
is a block diagram showing a structure of an imaging apparatus using a CCD image sensor.
FIG. 2
is a timing chart illustrating operation of the imaging apparatus of FIG.
1
.
A CCD image sensor
1
comprises a plurality of light receiving pixels, a plurality of vertical transfer registers, and, generally, one horizontal shift register. The plurality of light receiving pixels are arrayed with constant intervals on a light receiving plane, on which an optical image of an object is formed. Each light receiving pixel generates and accumulates therein information charges corresponding to the formed image. The vertical shift registers, each arranged to correspond to a light receiving pixel column, read information charges accumulated in the respective light receiving pixels for sequential transfer in the vertical direction. The horizontal shift register, arranged on the output side of the vertical shift registers, receives information charges from the plurality of vertical shift registers, and transfers them for every light receiving pixel row, whereby an image signal Y, the voltage value of which differs according to the amount of information charges accumulated in each light receiving pixel, is output.
A driving circuit
2
supplies various transfer clocks to each shift register of the CCD
1
in response to synchronous signals such as VD, HD, supplied from a timing control circuit
3
(described below). For example, in response to a vertical synchronous signal VD, the driving circuit
2
generates a frame transfer clock ØF, and supplies one to vertical shift registers. In response to a clock ØF, information charges accumulated in the plurality of light receiving pixels are taken into the vertical shift registers for every vertical scanning period. In response to a horizontal synchronous signal HD, the driving circuit
2
generates an accumulation transfer clock ØS and a horizontal transfer clock ØH, and supplies ones to the vertical shift registers and the horizontal shift register. In response to these clocks ØS, ØH, the vertical and horizontal shift registers transfer the information charges stored therein, so that information charges in the vertical shift registers are output for every horizontal light receiving row via the horizontal shift register. In response to a shutter timing signal ST supplied from the timing control circuit
3
, the driving circuit
2
generates a discharge clock ØD, and supplies one to a drain region of the CCD
1
, via which to discharge unnecessary charges. With the above arrangement, information charges accumulated in the light receiving pixels of the CCD
1
can all be discharged to the drain region. The time period from the end of a discharge clock ØD to the beginning of a frame transfer clock ØF, defined as a time L, correspond to a period for information charges to be accumulated in the CCD
1
, or an exposure time.
The timing control circuit
3
divides a reference clock of a predetermined cycle to thereby generate a vertical synchronous signal VD for determining a CCD
1
vertical scanning timing, and a horizontal synchronous signal HD for determining a CCD
1
horizontal scanning timing. For example, for the NTSC method, the timing control circuit
3
has a structure for dividing a 14.32 MHz reference clock by 910 to thereby generate a horizontal synchronous signal HD, and for dividing a resultant horizontal synchronous signal HD by 252.5 to thereby generate a vertical synchronous signal.
An integration circuit
4
is reset in response to a vertical synchronous signal VD, and integrates an image signal Y from the CCD
1
for every vertical scanning period to thereby generate integration information I, which is proportional to an average level of the image signal Y. An exposure determination circuit
5
compares, for every vertical scanning period, integration information I received from the integration circuit
4
and upper and lower values of a suitable exposure range, and raises either an exposure suppression signal CL or an exposure promotion signal OP according to the comparison result. Specifically, for integration information I exceeding the upper value, an exposure suppression signal CL is risen, while, for the integration information I not reaching the lower value, an exposure promotion signal OP is risen. An up-down counter
6
stores information of a timing for a shutter timing signal St to rise, by means of the number of a horizontal scanning line. Specifically, the up-down counter
6
is counted up in response to a rise of an exposure suppression signal CL, and counted down in response to a rise of an exposure promotion signal OP. That is, for every vertical scanning period V, a shutter timing signal ST is risen at a time when the number of horizontal scanning periods, the number being designated by the up-down counter
6
, have passed. A latch
7
latches a count value of the up-down counter
6
for every vertical scanning period in response to a vertical synchronism signal VD, and supplies the latched value information as exposure information D to the timing control circuit
3
.
In a solid-state imaging apparatus of the above structure, the up-down counter
6
is counted up or down for every screen according to the level of an integration value I of an image signal Y. This arrangement allows adjustment of an exposure time L for every vertical scanning period through extension or reduction in unit of one horizontal scanning period.
The above structure for exposure time adjustment, however, requires a certain amount of time before optimum exposure condition is can be attained for a solid-state image sensor when the power is switched on or brightness of the object is abruptly changed. That is, as an exposure time for a CCD
1
is extended or reduced at a predetermined rate for every vertical scanning period, a significant difference between the exposure time at the beginning of exposure control and an optimum exposure time prevents instant adjustment to the optimum exposure time, and might results in a long period being required to complete the exposure control operation. Although adjustment of an exposure time at a larger ratio for every vertical scanning period could hasten and thus complete an exposure control operation in a shorter time, such adjustment would be excessively sensitive to variation of object brightness, which may cause excessive extension or reduction of an exposure time, and resultantly makes unstable exposure control.
SUMMARY OF THE INVENTION
The present invention has been conceived to overcome the above problems and aims to achieve stable exposure control operation that completes in a short time.
Specifically, according to the present invention, there is provided a solid-state imaging apparatus, comprising a solid-state image sensor having a plurality of light receiving elements arrayed thereon, for accumulating in each of the plurality of light receiving elements information charges according to a received object image; a driving circuit for discharging the information charges accumulated in each of the plurality of light receiving elements of the solid-state image sensor, and for outputting, after a predetermined period, information charges accumulated in each of the plurality of light receiving elements whereby an image signal according to the information charges is obtained; first exposure information generating circuit for detecting a level of the image signal in a predetermined cycle to generate first exposure information which is increased or decreased based on a detection result; second exposure information generating circuit for calculating second exposure information based on the level of the image signal; selecting circuit for selecting either the first exposure information or the second exposure information; and timing control circuit for setting discharge timing and output timing to the driving circ

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