Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2001-10-24
2004-11-16
Blum, David S. (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
Reexamination Certificate
active
06818528
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to device manufacturing, and more particularly to a method of forming a plurality of apertures in a substrate, with each aperture having a predetermined depth, wherein at least two of the apertures have different depths associated therewith. More specifically, the present invention relates to a method of forming a plurality of trench isolation regions in a semiconductor substrate, with each trench isolation region having a predetermined depth, wherein at least two of the trench isolation regions have different depths associated therewith.
BACKGROUND OF THE INVENTION
The migration to vertical metal oxide semiconductor field effect transistor (MOSFET) cells for dynamic random access memory (DRAM) and embedded dynamic random access memory (eDRAM) has led to the requirement of trench isolation regions in array device areas which are shallower than in the support device areas. The array device areas are those regions of the semiconductor wafer that have devices that benefit from longer channel lengths. Thus, the array device areas typically contain the DRAMs and eDRAMs capacitors (and hence the access transistors to the capacitors). These circuits operate at higher voltages than the supports that generally, but not always, operate at lower voltages and consist of higher performance transistors.
In order to avoid floating well effects, which lead to data retention problems, the array device areas require trench isolation regions which are shallower (on the order of from about 100 to about 150 nm) than what has been customarily practiced in the semiconductor industry. On the other hand, the standard depth (about 250 nm) trench isolation is required in the support device areas to provide adequate isolation between source/drain (S/D) diffusions and adjacent wells. Prior art vertical DRAM cells using shallower isolation trenches in the array device areas generally require an additional critical mask to separately define support device isolation regions.
Examples of prior art that may form isolation regions having different depths include U.S. Pat. No. 4,988,639 to Aomura (“Aomura”), U.S. Pat. No. 5,679,599 to Mehta (“Mehta”), and U.S. Pat. No. 5,888,881 to Jeng, et al. (“Jeng, et al.”). These prior art methods are not cost effective since they require additional critical masks and/or use elaborate processing steps for forming isolation regions having varying depths.
Specifically, Aomura discloses a method of manufacturing semiconductor devices that requires the use of a separate critical mask for each isolation depth region desired. The use of a single critical mask to define isolation trenches having different depths is, however, not disclosed in Aomura. In addition to requiring the use of separate critical masks to define the variable depth trench isolation regions, the method disclosed in Aomura suffers from alignment sensitivity between the two isolation regions.
Mehta discloses a method for isolating regions of a circuit device in a semiconductor substrate. Specifically, Mehta discloses a structure having two types of isolation regions; trench isolation having a first depth and recessed local oxidation of silicon (LOCOS) isolation having a shallower second depth. Although openings in a masking layer for all isolation regions are formed simultaneously with a critical mask, a resist placeholder region is needed to protect the shallower isolation while the isolation trenches are etched. A maskless technique is then employed to process the shallow isolation without affecting the depth of the trench isolation.
Jeng, et al. disclose a process for fabricating a recessed field oxide area. The Jeng, et al. patent depends on the trench width to determine the type of isolation, i.e., trench isolation or LOCOS. The Jeng, et al. patent does not specifically disclose the formation of isolation regions of different depth, although that may incidentally occur as a byproduct of the process. The main objective of Jeng et al. is to provide trench isolation regions having either sharp corners and steep sidewalls or rounded silicon corners with sloped sidewalls. The method employed in Jeng, et al. includes a recess etch of the trench fill material of two types of trenches; a narrow first type trench and a wider second type trench, allowing the first fill material to be completely removed from the second type trench. The second type trench is then modified by using a LOCOS technique; while the first type of trench is partially protected from the LOCOS by the remaining first fill material.
In view of the above, there is an increased need for providing a cost effective method of forming a plurality of apertures, such as trench isolation regions, in a substrate, such as a semiconductor substrate, wherein at least two of the apertures have different depths.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a cost effective method for forming a plurality of apertures in a substrate, each aperture having a predetermined depth, wherein at least two of the apertures have different depths associated therewith.
A further object of the present invention is to provide a method which is useful in forming a plurality of trench isolation regions in a semiconductor substrate wherein at least two of the trench isolation regions have different depths associated therewith.
Another object of the present invention is to provide a method of forming a plurality of apertures, such as trench isolation regions, in a substrate wherein the alignment of the apertures is independent of the mask used in forming the same.
In broad terms, the inventive method for forming multi-depth apertures in a substrate comprises the steps of:
(a) providing a pad stack atop a surface of a substrate having regions for forming apertures therein, said pad stack including at least a top patterned masking layer;
(b) blocking at least one of said regions of said substrate with a first block mask, while leaving at least one other region of said substrate unblocked;
(c) forming a plurality of first apertures having a first depth in said unblocked region of said substrate using said patterned masking layer to define said plurality of first apertures;
(d) removing said first block mask; and
(e) forming a plurality of second apertures having a second depth in regions of said substrate that were previously blocked by said first block mask using said patterned masking layer to define said second apertures, while simultaneously increasing said first depth such that said first depth is deeper than said second depth.
In some embodiments of the present invention, a second block mask may be formed on a remaining portion of the regions of the substrate that were blocked by the first block mask prior to conducting step (e). After step (e) is performed, the second block mask is removed and a plurality of third apertures having a third depth are formed in regions of the substrate that were previously blocked by the second block mask using the patterned masking layer to define the third apertures, while simultaneously increasing the depth of both the first and second apertures. In this embodiment of the present invention, the first apertures have a depth greater than the second apertures, which, in turn, have a depth greater than the third apertures.
The above processing of blocking and forming a plurality of apertures may be repeated any number of times so as to provide different sets of apertures in the substrate that have varying depths. It is noted that the apertures formed later in the inventive method will be shallower than the previous formed apertures.
In a preferred embodiment of the present invention, the apertures are trench isolation regions and the substrate is a semiconductor substrate.
REFERENCES:
patent: 4495025 (1985-01-01), Haskell
patent: 4988639 (1991-01-01), Aomura
patent: 5298450 (1994-03-01), Verret
patent: 5340755 (1994-08-01), Zwicknagl et al.
patent: 5536675 (1996-07-01), Bohr
patent: 5646063 (1997-07-01), Metha et al.
patent: 5679599 (1997-10-01), Mehta
patent: 568
Divakaruni Ramachandra
Mandelman Jack A.
Abate Joseph P.
Blum David S.
Scully, Scott, Murphy and Presser
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